How to constraint clocks in Quartus?

[vsrpkumar]

I am into a design.In clock generation unit i have certain ripple clocks and gated clocks.i want to constraint them in quartus s/w .can anyone help me regarding this.I am in urgent need of it.Thanking you
kumar

 

[echo47]

clock constraints

That can be a nightmare! I suggest redesigning the project with synchronous logic to eliminate ripple clocks and gated clocks.

For more explanation, refer to this Altera paper, "Design Guidelines for Optimal Results in FPGAs"
**broken link removed**

or this one from the Quartus handbook, "Design Recommendations for Altera Devices"
https://www.altera.com/literature/hb/qts/qts_qii51006.pdf

 

[alt007]

Re: clock constraints

hi,
use the option auto gated clock conversion option in qu(at)rtus tools it may help u n some way.

regards
alt007

 

[yasser_shoukry]

Re: clock constraints

That can be a nightmare! I suggest redesigning the project with synchronous logic to eliminate ripple clocks and gated clocks.

Totally agree with you, ripple clocks may ruin your design if you are not professional.

 

[master.ro]

Re: clock constraints

Hello friends!
What is ripple clock ?
Thank you!

 

[anmolvlsi13]

clock constraints

Ripple clk will we generated when you r using Ripple (Asynch.)Counter in your design.
You can put the constraint by selecting CLEAR & Preset signal in your design.

Gated Clk is only useful for LOW POWER requirement.
Anmol