How to code a mathematical set equations using verilog

[dineshprasad]

verilog code for mathematical

hi,

I have to compare 2 mathematical sets( set has no's) and have to get 2 different results

1. The intersection of tehe 2 sets

2. The Union of the 2 set.

Can any one please guide me to how to code this in verilog HDL.

Thanks a lot in advance


dp

 

[echo47]

Please clarify: Sets of what? What are "no's"?
Perhaps give an example.

 

[soccer]

first, you must code those set that you have defined, then you can use the current logic operator to programing.

 

[dineshprasad]

hi ,

The example set may be 2 signals a and b
let
a={4,7} which means (4,5,6,7} (the set are continues and sequential series}
b ={5,9} which is expanded as {5,6,7,8,9)

a union b , should give a signal(out) c={5,7} which means {5,6,7}

Thanks

dp

 

[echo47]

I think you mean "a intersect b", not union. Yes?

How do you want to express the null set (no members common to both sets)?

Have you coded that in any other language? It sounds like a few comparison operators. That would be easy to translate to HDL.

 

[dineshprasad]

hi

yes "intersection" , but the result should be a set which has no's in set a, but not in set b.
I have not coded that in any other language till now, is there any pre defined function for this similar operations in verilog HDL

Thanks a lot
dp

 

[echo47]

Still not clear. Numbers in set a that are not in set b? Your example sets would give {4} not {5,6,7}.

I don't think any common programming language has built-in set manipulation functions. Same with Verilog. You'll have to write your own expressions using conditional operators such as < > >= <=. The Verilog syntax would be similar to C syntax.

 

[dineshprasad]

Thanks a lot........ it seems to be working....

dp