samiksha
Junior Member level 1
i'm designing an interrupt controller in verilog. the problem i'm facing is when our first interrupt acknowledgement (inta)signal comes, we'll write data on data bus. when 2nd inta comes another data shud be written nd similarly for the third inta. nw the point is how to check three pulses coming on the same signal inta. nd giving different output to data bus on three consecutive inta.
waiting for ur answers
thanku
waiting for ur answers
thanku