xtcx
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Hi friends!, I am using Spartan 3 (2000K gate) chip for my project. Xilinx ISE 8.2i
Doubt No.1
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During running synthesis, under "Device utilization", it shows "BRAM = 38\40 - 95%"
When I further ran PAR, there under "Logic Distribution",it shows "No. of BRAMs =26\40 - 65%"
Now here, which one should I consider?...In synthesis report it showed 95%,
whereas here it shows only 65%...Can I use more BRAM by considering the PAR results? or should I watch out for synthesis report too?...That means,only "2" BRAMS couldbe used as compared to Synthesis report, but "14" couldbe used from PAR report...If I proceed by using more than 2, will it generate error?...Or what shouldbe done?...I don't know...
Doubt No.2
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Similar to the BRAM case, the maximum frequency value is shown in synthesis report as 57.3 MHz ,but where should I find the PAR clock result?.Also could someone tell me which one should be taken in to consideration
...Please help....Thanks.
Doubt No.1
-------------
During running synthesis, under "Device utilization", it shows "BRAM = 38\40 - 95%"
When I further ran PAR, there under "Logic Distribution",it shows "No. of BRAMs =26\40 - 65%"
Now here, which one should I consider?...In synthesis report it showed 95%,
whereas here it shows only 65%...Can I use more BRAM by considering the PAR results? or should I watch out for synthesis report too?...That means,only "2" BRAMS couldbe used as compared to Synthesis report, but "14" couldbe used from PAR report...If I proceed by using more than 2, will it generate error?...Or what shouldbe done?...I don't know...
Doubt No.2
-------------
Similar to the BRAM case, the maximum frequency value is shown in synthesis report as 57.3 MHz ,but where should I find the PAR clock result?.Also could someone tell me which one should be taken in to consideration
...Please help....Thanks.