how to build two dual port ram ?

[lzh08]

how to build two dual port ram using the M4K?
i want to use the M4K to build two dual port ram,each dual port ram include 64k bit,total is 128k bit.

the following is the report after compile.
Total Memory bits:65536/239216.
why?i think the result should be 131072/239216.
how to build two dual port ram?
use "generate"?
---code
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity dualportram is
port
(
clk : in std_logic;
dout: inout std_logic_vector(7 downto 0)
);
end dualportram;

architecture action of dualportram is

component lpmramdp_1
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
wren : IN STD_LOGIC := '1';
wraddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component;

component lpmramdp_2
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
wren : IN STD_LOGIC := '1';
wraddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end component;

signal wrCount_1 : std_logic_vector (11 DOWNTO 0);
signal rdCount_1 : std_logic_vector (12 DOWNTO 0);
signal dataIn_1 : std_logic_vector (15 downto 0);
signal wrCount_2 : std_logic_vector (11 DOWNTO 0);
signal rdCount_2 : std_logic_vector (12 DOWNTO 0);
signal dataIn_2 : std_logic_vector (15 downto 0);
--signal dataOut : std_logic_vector (7 downto 0);

begin
process(clk)
begin
if rising_edge(clk) then
wrCount_1 <= wrCount_1 + 1;
rdCount_1 <= rdCount_1 + 1;
wrCount_2 <= wrCount_2 + 1;
rdCount_2 <= rdCount_2 + 1;
end if;
end process;

u1: lpmramdp_1
port map
(
data => dataIn_1,
wren => '1',
wraddress => wrCount_1,
rdaddress => rdCount_1,
clock => clk,
q => dout
);

u2: lpmramdp_2
port map
(
data => dataIn_2,
wren => '1',
wraddress => wrCount_2,
rdaddress => rdCount_2,
clock => clk,
q => dout
);
end;

 

[jcchan]

To use synplicity to synthesis