How to build a functions package in Verilog

[hamzah.aaaa]

verilog package

Hello everyone,

i want to build a verilog package that contain functions, and i include it in any other verilog file and use its function in any module in this file.

I want to build something like

package Package_name  is

-- ...
-- functions declaration ...
-- ...

end Package_name;

In VHDL.
but i want it in Verilog.


Many thanks.

 

[Mkanimozhi]

build in functions

Hi,
write the function you want to use global in separate file within a module and use that file using `include "filename.v" in you needed main module and function calling is same as we do.

Kanimozhi.M

 

[Rahul Gupta]

Re: build in functions

Hi,
write the function you want to use global in separate file within a module and use that file using `include "filename.v" in you needed main module and function calling is same as we do.

Kanimozhi.M

Hi,
I still couldn't able to include my package file in verilog module. I am trying to add package file(codec_package.v) in verilog module ( DE1_TOP.v ). I am instantiating it with
`include "codec_package.v" in verilog module ( within module).
but while analysis and synthesis, the compiler is giving error saying "Error (10170): Verilog HDL syntax error at codec_package.v(7) near text "endmodule"; expecting ")".

module codec_package (
~~~~
~~ Function declaration
~~~
endmodule

Is that i can't use module for package ? what should i use to declare a package file in verilog ? any tutorial for verilog package declaration ?
I have done most of my system design on vhdl and i am bit new to verilog.

Thanks and regards,
Rahul Gupta

 

[imbichie]

can you post your code here, then its easy to find the syntax error.

 

[mrflibble]

Depends on the verilog standard you can use, see this bit.

Short version: verilog-2001? You're boned.

 

[dave_59]

You should have been able to write a Verilog module with functions declared inside them

module my_package;
function integer add(integer a,b);
begin
  add = a+b;
end
endfunction
endmodule

Then you need to instantiate my_package, and you can call my_package.add(x,y); But some synthesis tools may not allow this kind of hierarchical reference. You did not show enough code that would explain the error you are getting.

In SystemVerilog, you would write this as

package my_package;
function integer add(integer a,b);
begin
  add = a+b;
end
endfunction
endpackage

Then you import the package with import my_package::* and now you can call add(x,y). Or you can skip the import and call the function explicitly with my_package::add(x,y).

 

[Rahul Gupta]

You should have been able to write a Verilog module with functions declared inside them

module my_package;
function integer add(integer a,b);
begin
  add = a+b;
end
endfunction
endmodule

Then you need to instantiate my_package, and you can call my_package.add(x,y); But some synthesis tools may not allow this kind of hierarchical reference. You did not show enough code that would explain the error you are getting.

In SystemVerilog, you would write this as

package my_package;
function integer add(integer a,b);
begin
  add = a+b;
end
endfunction
endpackage

Then you import the package with import my_package::* and now you can call add(x,y). Or you can skip the import and call the function explicitly with my_package::add(x,y).

Hi,
As i need package file in verilog and i am not sure how to write it in verilog, here is the equivalent vhdl code for that. Please help me write the equivalent in verilog.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;

package ft_package is

type complex is record
r : signed(15 downto 0);
i : signed(15 downto 0);
end record;
type signed_vector is array (0 to 15) of signed(7 downto 0);
type comp_array is array (0 to 15) of complex;

end ft_package;
---

and what i am writing is as follows :-
---
module ft_package (
type complex{
signed [15:0] r;
signed [15:0] i;
};

type signed_vector signed [7:0] a; // a ?
type comp_array complex b; // b ?

endmodule
---

Please let me know if i am wrong (and about a and b)
Thanks,
Rahul Gupta

 

[dave_59]

The equivalent SystemVerilog code is close to what you would write in C.

package ft_package;

typedef logic signed [15:0] int16;
typedef logic signed [7:0] int8;

typedef struct {
   int16 a;
   int16 b;
} complex;

typedef int8 signed_vector[0:15];  // or just [16]
typedef complex comp_array[0:15]; 

endpackage : ft_package

The intermediate types int8 and int16 aren't strictly necessary, but make the code much easier to read.

Note that you cannot share typedefs across modules; they must be put into packages if you want to use them in multiple modules.

 

[Rahul Gupta]

The equivalent SystemVerilog code is close to what you would write in C.

package ft_package;

typedef logic signed [15:0] int16;
typedef logic signed [7:0] int8;

typedef struct {
   int16 a;
   int16 b;
} complex;

typedef int8 signed_vector[0:15];  // or just [16]
typedef complex comp_array[0:15]; 

endpackage : ft_package

The intermediate types int8 and int16 aren't strictly necessary, but make the code much easier to read.

Note that you cannot share typedefs across modules; they must be put into packages if you want to use them in multiple modules.

Thanks for your reply Mr. Dave Rich. I am one more doubt. I heard that we can't use vhdl package in verilog and verilog package in vhdl so that why i am trying to write different packages separately. Now, as you mentioned the package in systemverilog, can i use it as package for verilog because when i tried to find the way to write verilog package file in verilog, i found all of them in systemverilog ( maybe google took the later half "verilog" while searching). So my question is if we can use systemverilog (.sv) file (package file) for verilog program (.v) file/module ? or in other words, can i use this systemverilog package in my verilog module's project ?

 

[dave_59]

The answer depends on which tools you are using. Modelsim/Questa allows you to mix the type information in packages between the VHDL and SystemVerilog languages. SystemVerilog is an updated version of Verilog, not a separate language. Most tools that support SystemVerilog already support packages.

 

[Rahul Gupta]

Hi,
I think there is some problem in instantiating. After compiling, it is giving error as " syntex error" at each line of package(.sv)?
Here is my codes (after removing unnecessary things):-

file : DE1_TOP.v
--
module DE1_TOP
(
CLOCK_24, // 24 MHz
CLOCK_27, // 27 MHz
CLOCK_50, // 50 MHz

AUD_ADCLRCK, // Audio CODEC ADC LR Clock
AUD_ADCDAT, // Audio CODEC ADC Data
AUD_DACLRCK, // Audio CODEC DAC LR Clock
AUD_DACDAT, // Audio CODEC DAC Data
AUD_BCLK, // Audio CODEC Bit-Stream Clock
AUD_XCK, // Audio CODEC Chip Clock
);
input CLOCK_24; // 24 MHz
input CLOCK_27; // 27 MHz
input CLOCK_50; // 50 MHz

inout AUD_ADCLRCK; // Audio CODEC ADC LR Clock
input AUD_ADCDAT; // Audio CODEC ADC Data
inout AUD_DACLRCK; // Audio CODEC DAC LR Clock
output AUD_DACDAT; // Audio CODEC DAC Data
inout AUD_BCLK; // Audio CODEC Bit-Stream Clock
output AUD_XCK; // Audio CODEC Chip Clock

`include "codec_package.sv"
//import codec_package::*; // don't need to write this one?

endmodule

--

and package code is same as above :-

file: codec_package.sv
--
package codec_package;

typedef logic signed [15:0] int16;
typedef logic signed [7:0] int8;

typedef struct {
int16 r;
int16 i;
} complex;

typedef int8 signed_vector[0:15]; // or just [16]
typedef complex comp_array[0:15];

endpackage

--

If you try to compile the above, you will find the syntex errors.

Rahul gupta

 

[dave_59]

The package gets compiled separately from the module, not included inside the module. See https://go.mentor.com/package-import-versus-include and the article it references.

Also please use the simpler port declaration style where you only need to write each identifier once on a single line.

import codec_package::*;
module DE1_TOP
(
  input CLOCK_24, // 24 MHz
  input CLOCK_27, // 27 MHz
  input CLOCK_50, // 50 MHz

  inout AUD_ADCLRCK, // Audio CODEC ADC LR Clock
  input complex AUD_ADCDAT, // Audio CODEC ADC Data
  inout AUD_DACLRCK, // Audio CODEC DAC LR Clock
  output complex AUD_DACDAT, // Audio CODEC DAC Data
  inout AUD_BCLK, // Audio CODEC Bit-Stream Clock
  output AUD_XCK // Audio CODEC Chip Clock
);
...
endmodule