How to back annotate SDF to VHDL?

[swgchlry]

My design is wirote in VHDL, but SOC Encounter read a verilog gate netlist file.
After the synthesis, Synopsys DC can generate gate-level netlist in both vhdl and verilog format. But I want to do post-layout simulation with VHDL gate-level netlist, is it possible? Does the sdf file could be annotated to a vhdl gate-level netlist file?

 

[chen_hongbin]

I have the same question. Can somebody answer it?

 

[jtbaron]

u can write module in verilog format,and componet in your top-level testbench.