how to avoid unknown state during post simulation?

[xv_ning999]

in my recent design, there were some cross-clockdomain signals.when i was doing post simulation these signals got unknown state due to the hold time violation when they pass through different clock domains. and then these unknown states propagated through my design.They at last make my post simulation unrunnable.I take masures to avoid meta-stable in my RTL coding. But is there anyone can give me some advice about how to control these known states to propagate in my post simulation?

 

[yln2k2]

Hi ,

Clk Crossing domains need to taken care correctly by design .
if you have a violation in your simulation should proceed further without any issue .

One of the practice is disable timing for those flops in SDF . just make corresponding flop hold timing checks to "0" . This will solve your issue .

But before you do this you need to enalize
- Your RTL is taken care for clk crossing , so hold violatuion ( which can happend in real time) should not effect your functionality .
- If you have synchronization clk and if you get hold violation on first you can go ahead and do a SDF patch ( you can make holdtime check to "0") .



Thanks & Regards
yln

 

[jjww110]

1. all signal has initial value
2. no violation

 

[Zeng Jie-jun]

It should be dealed with two different cases.
1. Real violation, debug and find the reason to cause x and solve it.
2. No a function issue and only the simualtion cause it. --- disable it to transfer to next stage. there is a xfilter parameter register in some library, you can set xfilter = 1 to disable x state.