How to arrange power and gnd lines in floor-plan?

[rod_wu]

My design include memory and analog IP . I don't know how to arrange power and gnd lines in floor-plan. is it separate digital and analog power lines? It is important to design power-gnd plan on ASIC. Who have reference data or book?

 

[Mr.Cool]

here is a link to "The Art of Analog Layout" . maybe this will help

h**p://w*w.mcu.cz/atm/index.php?&direction=0&order=&directory=eBookNew/Electronics/Art%20of%20Analog%20Layout%20-%20Hastings

note that you must register with website before you can download from them

Mr.Cool

 

[rakko]

You basically have to make sure to keep analog and digital rails isolated from one another. All hardmacro and memory blocks need to have a vdd/vss pair ring around them. memories are always on the side or corners of your chip. put a pair of vdd/vss ring around your design. this is usually called core power ring. run a pair of vertical vdd/vss every 100 micron. this is called the power straps and on either side taps into the core power ring. put a pair of vdd/vss around every analog block and strap these analog rings (using a pair of vdd/vss) and run them to your package vdd/vss rings keeping in mind that in every place a digital vdd/vss crosses analog vdd/vss straps, then you need to cut the digital vdd/vss on either side of the analog crossing to isolate the analog from digital noise. you need to dedicate pins on your chip for analog power and ground. Now we come to the most time consuming part of this, HOW THICK SHOULD YOU MAKE all these rings/straps. The answer is this is technology dependant. Look into the packaging documentations, they usually have guidelines for how to calculate the thickness of you power rings. Some even have applications that calculates all this for you and makes the cuts for analog/digital crossings.

 

[electronrancher]

what is an analog/digital cut? a jump to metal 2? can you scan me a drawing or something.. ?