brakchus
Newbie level 4
Hi, I'm working on layout of IO buffer and wondering how is connection of 1.2V and 3.3V nmos transistors to substrate realized? If 1.2V and 3.3V nmos transistors are connected to the same substrate, how does it has to esd reliability? Pmos are connected to separated nwells. I'm using UMC 130nm. Should I connect nmos to sub using twell?