HOW MUCH GATES PCI express core will take in FPGA?

[zafir]

Dear engineers,

Please help me to get out of these problem.

1). My project supervisor give me task to determine how much gates pcie core will occupy (this core would be written by myself as a final year project, may be I would take some references and help from xilinx pcie core, if they are provided for free)

2) I had no experience of running Microblaze core but in our final year project (undergraduate level project) we have to use this core, We are asked to find if it is possible that we can place the code for microblaze processor on the same Flash PROM where we keep the configuration Bit file of FPGA.

3). In our final year project we have to design fpga customized board for following purpose. In FPGA, microblaze core would be running and it schedules pcie core to perform communication with Host PC (where labwindows based application would be running) the board will have interface to 1553 bus so there would be a 1553 core in FPGA to perform communication on avionics bus. Basic purpose of this fpga card is to provide interface between host pc and 1553 bus. Now I need your expert opinions to select FPGA chip with enough gate count to do all these tasks easily and economically we already have spartan 3 1500k gate chips, Are they sufficient enough for our task or we have to go for more newer and powerful chip family. My supervisor is saying look for spartan3AN but I don't know that SPARTAN 3AN is capable of doing all these jobs because we are writing core for the first time so we know that our core will not be so much optimized and it may waste some extra silicon of FPGA. 4). Please refer me any learning materials or any thing for successfully writing OPTIMIZED pci e core(with in 3 months), my current status is that I only know fundamentals of VHDL programming and I performed some practicals on spartan3e1600k gate kit and I also used picoblaze controller core. IF xilinx is providing some help related to my project (pci e core microblaze core etc) then please let me know. Please help me. THANKS AND SORRY IF I POST THIS MESSAGE IN WRONG CATEGORY OR IF IT IS ALREADY POSTED MESSAGE

Regards
Zafir Hafeez

 

[FvM]

To give a reference number, the Altera PCIe core will take 11300 logic elements (4 input LUT), 4500 registers and 240kBit of embedded RAM with Cyclone III, which is mid-scale FPGA, that should be roughly comparable to Spartan 3. For details, review the PCIe core manual, downloadable from altera.com. I guess, that Xilinx will have also resource count specifications in their manuals.

 

[permute]

1.) look at the PCIe "coregen" datasheets, which list resource usage and other info for PCIe. Also look at the reference designs. The FPGA's that have PCIe hard-ip should be fairly safe. keep in mind that PCIe needs the 3Gbps "GTP/GTX" or "MGT" tiles.
2.) yes, though you will need to make sure the bit ordering is correct for both programming and data cases. You may want a fast flash (like platform flash XL) to ensure the FPGA programs quickly at boot.
3.) You really would be better off using either ethernet or USB. Likewise, 3months to design, produce, and develop for a custom board is a very difficult thing to do.

It may actually be easier to get a microprocessor dev board to work.

 

[zafir]

Thanks for replying and giving your opinions.
I actually have to cover pci express part of our project in three months (maximum)

Regards
Zafir Hafeez

 

[xtcx]

To give a reference number, the Altera PCIe core will take 11300 logic elements (4 input LUT), 4500 registers and 240kBit of embedded RAM with Cyclone III, which is mid-scale FPGA, that should be roughly comparable to Spartan 3. For details, review the PCIe core manual, downloadable from altera.com. I guess, that Xilinx will have also resource count specifications in their manuals.

Do soft IPs for PCIe available for FPGAs too?. I heard only hard IPs are available. Correct me if wrong!!!

---------- Post added at 18:20 ---------- Previous post was at 18:19 ----------

I thought it might be hard to achieve through soft IP since it may need some clock multipliers which are not built in like other PLLs etc...

 

[FvM]

In addition to a soft IP, Gigabit transceivers with respective infrastructure for clock generation and recovery are of course required.

The above stated PCIe soft IP core resource requirement is valid for FPGAs with Gigabit transceivers, e.g. Arria GX or Stratix III GX. Newer FPGAs like Cyclone IV GX, Arria II GX or Stratix IV GX have built in dedicated PCIe hardware.