how many samples should i use for generating sin wave?

[richardhuang]

i am designing the IF demodulator, i will generage an sine and cosin wave(NCO), the frequency is 57M and is same as carrier, how many samples is proper for the generating( of course it shoud match the Nyquist theory)?

 

[mondunno]

hi

carrier frequency is 57M, but whats the bandwidth of the message signal? now 57+max b/w is the max freq component, Sampling freq must be well beyond Twice of this max freq, and not carrier freq alone... anyway i cant tell u much on what exact frequency...

 

[echo47]

For conventional DDS topology, it's a tradeoff between oversampling (many samples per cycle, requiring more expensive digital logic and DAC) followed by a simple inexpensive analog filter, or sampling close to twice Nyquist and using an expensive sharp-cutoff analog filter.

For example, you could sample at only 120 MHz (slightly more than two samples per cycle), but then you would need a very sharp analog filter to separate the desired 57 MHz signal (Nyquist-3MHz) from the first unwanted spur at 63 MHz (Nyquist+3 MHz). Also, the sin and cos filters would need to be well-matched to maintain the 90 degree phase difference.

I usually begin by choosing a tolerable amount of analog filter complexity, and then calculate the minimum sample rate for the unwanted spurs to be removed by that filter. If the resulting sample rate is too expensive or too easy, I'll change the filter complexity and try again.

 

[FvM]

Hello,

to my opinion, the problem isn't necessarily related to Nyquist theorem, at least when the input is already band limited, which is typical the case at the point of IF demodulator. The basic requirement is that you are must be able to extract the quadrature components when downmixing to baseband.

An IF signal with spectral components from DC up to carrier frequency plus signal bandwith/2, could be e. g. sampled by a single ADC at exactly the fourfold carrier frequency. Demodulation could be reduced to simple decimation in this case . It could operate also at different sample frequency, at least sufficient above double carrier frequency (here you have Nyquist), but then requiring multiplication of ADC output signal with NCO generated carrier, allowing e. g. frequency fine tuning without changing the sampling clock.

But if the IF is bandlimited, to fc +/- bw/2, then Nyquist criteria doesn't apply to maximum frequency fc+bw/2. Instead it applies to bandwidth, allowing undersampling without loosing information.

Regards,
Frank

 

[echo47]

Yes, IF bandwidth sampling is a wonderful way to simplify a receiver design.

He may really need the 57 MHz quadrature sinewave for some unspoken reason. Maybe he can elaborate.

 

[FvM]

A alternative, straightforward design without any NCO would use two ADC sampling at 57 MHz with 90° phase shifted clocks, undersampling that requires only moderate IF filtering.

 

[richardhuang]

The maximal BW is about 8M, and Fs = 180M, the IF signal come from the output of tuner.
i generated the sin wave by look up the table which genetated by matlab tool.i can use the table of 128 or 256 or angles per circle or 64 phase per quadrant.
my quesiton is here how many items i shoud choose for the tables? 128?256?

 

[FvM]

Hello,

as pointed out in the discussion, 180 MS/s wouldn't be actually necessary, but if available, could ease IF as well as output filtering. Regarding the NCO look-up-table resolution, Matlab is a wonderful tool to evaluate the effect of rounding errors.

I can't exactly forsee the effect, but I would expect significant reduction of SNR with a 256 word table. I think, the table address resolution should roughly correspond to ADC resolution, as long you don't use interpolation. The basic point is to which resolution you effectively truncate NCO accu when generating the reference signal.

Mathematically, you can convert phase quanization noise generated by limited table resolution into reference signal amplitude noise, finally convert into additional output noise. In Matlab you simply have to perform a FFT on simulated output signal.

Regards,
Frank

 

[echo47]

Here's a sneaky shortcut. 57/180 equals 19/60, so use a 60-word sine ROM containing 19 sinewave cycles. By clocking it at 180 MS/s, you get exactly 57 MHz with no phase quantization error. (However, this shortcut isn't good if you need other frequencies besides 57 MHz.)

Here is a helpful document -- the data sheet for Xilinx's "DDS Compiler Core". Although the DDS core is intended for FPGA, the data sheet describes practical DDS design issues and techniques, including phase quantization (sine ROM size) and phase dithering.
**broken link removed**

 

[richardhuang]

Thanks all of you!your suggest is helpful