How many "capture"s in scan vectors ?

[leeguoxian]

Generally speaking, there are three types of capture procedure .
1. capture (no clock pulse)
2. capture_clk (test clock pulse)
3. capture_rst (reset pulse)

For the first pattern, it shift in certain vectors and shift out to check if scan chains works well, so we use "capture" procedure .
But actually, I found out that there were more than one "capture" procedure .

Why there are more than one "capture" procedure ?
What's the purpose of other "capture" procedures excepting the first ??

Thanks

 

[kbulusu]

not sure if I understood your question correctly..there are only 2 states in which the scan works..shift and capture cycle..in shift cycle, when the test clock is applied, it shifts in the test vectors and during the next cycle , they are shifted out..in capture cycle, the values of the test vectors stored in the FF are read ... people give different names, but as such there are only two states in simple DFT..

 

[pratap_v]

if i am correct
one for testing the combinational logic and other for testing the flipflops.
please correct if i am wrong.

 

[sparso]

I may not be getting your question right but I think what you are asking is why do you see multiple capture
sequences in a scan vector?

If that is the case,
I think you always concatenate multiple patterns in a test vector ..hence you would see multiple capture
sequences.

 

[leeguoxian]

I think the whole scan process would be like this:

pattern 0 : load_unload capture
pattern 1 : load_unolad capture_rst
pattern 2 : load_unolad capture_clk
pattern 3 : load_unolad capture_clk
pattern 4 : load_unolad capture_clk
...
...
...
pattern n : load_unolad capture_clk
pattern last : unload

I think there should be only one "capture" when using basic scan engine in Tmax .

But actually the patterns came out would be like this:
pattern 0 : load_unload capture
pattern 1 : load_unolad capture_rst
pattern 2 : load_unolad capture_clk
pattern 3 : load_unolad capture_clk
pattern 4 : load_unolad capture_clk
...
...
pattern m : load_unload capture
...
...
pattern n : load_unolad capture_clk
pattern last : unload

There is a "capture" in pattern m, my question is :
why there is a "capture" procedure , not a "capture_clk" ???

 

[dr_dft]

The extra capture in pattern m can detect additional faults on SE (scan_enable) pin of each flip-flop and some clock gating elements that have been disabled using scan_enable.

 

[leeguoxian]

The extra capture in pattern m can detect additional faults on SE (scan_enable) pin of each flip-flop and some clock gating elements that have been disabled using scan_enable.

I still don't get it.

If there is a SA0/SA1 fault on SE pin of one flip-flop, how could the design pass the previous patterns (before pattern m)?

 

[dr_dft]

If there is a SA0 on SE pin, shift pattern will detect it immediately. However, if there is a SA1, the only way to detect it is when D pin is different from SI pin, which in general may be easy to achieve, but not always without the proper pattern on D.

 

[cheelgo]

If there is a SA0 on SE pin, shift pattern will detect it immediately. However, if there is a SA1, the only way to detect it is when D pin is different from SI pin, which in general may be easy to achieve, but not always without the proper pattern on D.

hi dr_dft,
you explain the truth.
many thanks,
cheelgo

 

[leeguoxian]

If there is a SA0 on SE pin, shift pattern will detect it immediately. However, if there is a SA1, the only way to detect it is when D pin is different from SI pin, which in general may be easy to achieve, but not always without the proper pattern on D.

hi dr_dft ,
If we wanna detect the SA1 fault on SE pin of each filp-flop, we should drive SE to 0 and capture the output , right ?
But in the "capture" process, Scan_Enable is 1.

 

[dr_dft]

leeguoxian,
SE=1 during shift, not capture.
During capture, SE=0 which selects the D path to be captured. If there is a SA1 fault on SE, the SI pin will be selected instead. So detect a SA1 fault on SE, we need to be in capture mode (SE=0) and D has to be different from SI.

 

[leeguoxian]

leeguoxian,
SE=1 during shift, not capture.
During capture, SE=0 which selects the D path to be captured. If there is a SA1 fault on SE, the SI pin will be selected instead. So detect a SA1 fault on SE, we need to be in capture mode (SE=0) and D has to be different from SI.

hi dr_dft ,
I agree with u .
But in pattern m, SE is 1 during capture, and there is no clock pulse.
In pattern m , it shift in certain pattern ,
and in pattern m+1 , it just shift out the pattern that shift in in pattern m .
That is why I feel confused . Why SE is 1 in capture process, and no clock pulse??

 

[dr_dft]

I see your confusion now.
This pattern is detecting SA0 on SE pin. Although you may argue that the shift cycle should already cover this, a combinational ATPG does not count on it.
Even though an ATPG tool will simulate the shift process to make sure the chain is intact, it does NOT usually do full fault simulation during shift simulation, therefore, many faults that may be covered by pure shifting may not be dropped.
In a combinational ATPG, only faults detected during the capture cycle are counted. Therefore, the pattern that you have described is used to detect some faults on SE and clock gating cells.

 

[maxsnail]

good,I also got it.
thank.