[SOLVED] How latch up can be avoided by increasing the rise and fall delay transitions?

[kishanb]

Hi all
Can anybody tell me how latch up can be avoided by increase the rise and fall delay transistions ?
why does the threshold voltage increase when i place my transistor close to the well ?



Thanks and regards
Kishan.b

 

[erikl]

Re: Well proxi and latch up

... why does the threshold voltage increase when i place my transistor close to the well ?

See this paper: View attachment Implications_of_Proximity_Effects_for_Analog_Design.pdf

 

[dick_freebird]

I=C*dV/dt. That's the current that some portion of, will be
pushed into the wells and substrate to potentially become
the trigger current for your latchup SCR. Slower is less and
hopefully low enough that the tie resistances can hold the
local voltages below Vbe (worst at high temp where R goes
up and Vbe goes down).

But if you are this close to the edge, that's not a happy
place. Focus more on decent tie density / proximity.

 

[kishanb]

Thank you guys