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hi all,
can any one tell me about the setup margin.how it effect the timing.
if i change setup margin from 0.5 to 0.6,what will happend
please help me
thanks
Usually setup margin is given for tolerating the difference seen in P&R tool and STA tool. This is like introducing some pessimism in P&R tool so that we can close the design with some 100ps setup or hold margin.
Regarding timing it means we are closing the design with less slack. sometimes many paths will be violating if we increase the setup margin.
if you only use setup margin in timing opt but remove in STA,this is used for overconstraint to opt,if used this in STA,maybe take fabracation into account.
See when you synthesize the dsign and see the synthesis report you will find that net delay also come into picture. setup margin increase will allow better timing as the margin time is increase. What we mean by it is we have .5 time unit more that the circuit will show setup time violation.
hi all,
can any one tell me about the setup margin.how it effect the timing.
if i change setup margin from 0.5 to 0.6,what will happend
please help me
thanks
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