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you have to use command "set_timing_derate" to set ocv derates.
please check the command help for setting ocv numbers for setup and hold.
And also for different corners.
RC extraction doesn't need ocv numbers. it is independent of OCV.
RC extraction extracts R and C numbers of the nets based on the L and W. for this tools use R&C tables from foundry.
Where as OCV numbers are applied during STA. These are applied on the extracted circuit and timing is analysed.
What does mean "Corner"? Is it referenced to a special RC-extraction?
Vendor lib cells [std cells] have min/max delays representing timing variations between chips and OCV derate factors representing delay variations inside the same chip.
What about the nets? Besides OCV derate factors, what additional delay variations they may have?
Sorry for the confusion.
The corner i mean is operating condition. i.e max and min conditions. In max we check setup which is crucial. And in min we check hold.
std_cells will have min/max delays. But i am not sure of OCV derates
Derate values you can apply for nets also using the command set_timing_derate.
What's about the sentence "Design should be checked in as many corners as possible. Sometimes SignOff checks involve timing checks in up to 12 corners"?
So, if a vendor provides 3 timing libraries for MIN, TYP and MAX conditions, there are only 3 corners?
As for RC-extraction, there only one since each net has a final Length and Width and a final number of driven cells/other nets. Correct?
As for OCV checks, lets say we would choose 0.8 and 1.2 derate factors.
These are the following terms we will re-define
1. corners =extraction corners [it may vary from node to node. The number of extraction corners are defined by Foundry.]
2. checks = setup and hold [ transition, cap and fan-out will be checked anyway]
3. Derates= 1 sign-off values each for setup and hold.
4. Libraries = let us assume 3 type -MAX, MIN and TYP
If you want to calculate the Number of STA runs for sign off = [(Number of extraction-corners) * (Number of Libraries)]
In each run both setup and hold will be checked.
If you consider modes, then formula will become = Number of STA runs for sign off = [(Number of extraction-corners) *(Number of Modes) * (Number of Libraries)]
"it may vary from node to node" - so, what is node? Do you mean a technology node (45nm, 25nm, ...)?
" number of extraction corners are defined by Foundry" - how many extraction corners are usually used for 45nm libs?
"extraction corners" - are we talking about delays over nets? After P&R all the nets (their length, width, etc) are known, so all the delays over these nets are also known, so why more than one RC extraction is required? Are you talking about RC extractions for different PVT (MIN/MAX or BC/WC)? So, if there are only two PVT conditions, how RC-extractions might be more than two? Number of PVT std libs = Number of possible RC extractions?
As for TYP libs, does anybody use them? What for?
"If you consider modes, then formula will become" - what modes do you mean? I know the PVT and OCV modes (is PVT mode?), what do additional modes exist?
During the P&R, yes we know the length and width of the nets. But during manufacturing no body is sure, what is the length and width.
There are some variations. So the foundry release the extraction corners files and ask us to close the timing in these corners.
for 45nm, please see the foundry guidelines for corners. This info is confidential.
TYP libs will be used by every one. We have to sign-off with this too. We use chips under TYP only right. so we need to know the speed of our chips TYP.
Modes:
There are many modes for a chip. To name a few : Functional, test, BIST and so on.When we time it we have to close the timing in all these modes.
for this modes, SDCs will vary.
pandit.vlsi,. thanks for your commences, but I still have some questions...
I now how looks like WLM, NLDM files, but never seen the nxtgrd (rc-extraction) files... Could you please provide more details how it looks like and how it works?
What's the reason to check timing with TYP delay if they check it with MIN and MAX? Could you provide a case where the timing check would fail in TYP delay and meat in MIN and MAX?
As for different Chip Modes (Functional, Test, etc), why different SDC are required? Is this because some paths might be false in some modes and the frequency might be different in the different modes?
1. nxtgrd files are binary files. It is get any info by opening it in a text editor.
2. Yes you are right, if the timing is closed in MIN and MAX, there is a less possibility that in TYP timing will fail.But how to know the timing of the chip in TYP condition. You will not operate every chip in MIN and MAX conditions, isn't it?
3. Yes you are right. For ex: in functional mode, between flop there is a timing path between Q of first flop to D of second flop. In test mode there is a timing path between Q of first flop to SI of second flop.
Due to this SDC will be different.
Typical libraries are also very important.
Different libraries have dirrent lookup tables for the delay values and different derating factors too.
The skew of a clock could differ and it is not necessary that if it is met in best and worst conditions it will be met in typical too. Thats owing to the skew and derating factors.
Hence, it is important to check it in different corners.
Now, let us say that func, scan-shift and at-speed passed in all corners but MBIST has a path going to RAM which had 32buffers and each one in typical corner gave a delay of 1.2ps . Te derating factor is also 1.2 then total delay it sees is 1.2X1.2 = 1.44
Hence, every mode and every corner has to be checked.
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