How do I create a 1 us clk

[ntropy]

I want to create a 1 us clk signal. I have the Spartan 3E board that has a 50 mhz clk.

Thank you for your help

 

[JacquesKleynhans]

Well you could use a PLL to drop it down to 1Mhz, or use a counter that divides the main clock down to 1 Mhz

 

[mrflibble]

As JacquesKleynhans says, use a PLL or a counter.

In case of the spartan-3E you could use the internal DCM for the "PLL" option, but this does take a bit more effort than a counter. I generally only use the DCM on spartan-3E if I need a higher freq than the onboard oscillator provides.

Personally I'd go for the counter, since the DCM might give you some, uhm, interesting learning experiences you might not need right now. For the counter, lookie here for plenty of verilog examples.

 

[matbob]

Hi mrflibble,

Spartan3e DCM can't support that low freqs. The lower limit is 5MHz. You have to implement a counter after that.

 

[mrflibble]

Hi matbob,

Excellent point! Just checked the datasheet and indeed, for the 3E it's 5 MHz - 300 MHz. So I guess ntropy is lucky. Now he won't even be tempted to try the DCM first. Just divide by 50 using a counter.

 

[dilinx]

its better if u can use DCM or PLL for FPGA implementation, because if u implement clock division module as a counter it will take data path in FPGA (in FPGA clock is given a special care and routed in special paths) and hence chances of timing violation is more.....this (DCM or PLL) will improve maximum operating frequency of your design....