How do I control verilog "parameter" from VHDL TB?

[kelvin_sg]

My design hierarchy is

TB.vhdl 
---->ip_TOP.v 
       ---->ip_Module.v 
              ---->ip_memory.v

in which the ip_memory is parameterized in ip_Module.v, not in ip_TOP.v

module ip_memory (a,b,c);
parameter INIT_ARRAY = 1'b0; //defult value
// The INIT_ARRAY renders the ip_memory to read some initialization data.. 

blah blah.. 

endmodule

Both the IP and the TB are external so minimum modification of the RTL is allowed..
With ncsim 8.2, what can one do to fix that?
ncvlog +defparam doesnt seem to traverse across the hierarchy..