Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Any ADC can be interfaced with FPGA, either fast or slow, using parallel or serial protocols. But it's not ready to use, you need to write the respective interface logic.
Decide about your specification (resolution, speed, number of channels etc.), choose an ADC chip, design the interface.
Some FPGA eval kits are implementing a "poor mans" sigma delta ADC by using a FPGA differential input and an output pin providing feedback through a RC circuit.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.