AzatSG
Newbie level 2
Hi)
I have a signal with bandwidth about 150Mhz and central frequency 200 Mhz.
I need to divide it into 5 separate parts. So I want to down convert them by different frequency reference signals. Is it possible using DDS core from Xilinx core generator?
Any ideas...thanks
I have a signal with bandwidth about 150Mhz and central frequency 200 Mhz.
I need to divide it into 5 separate parts. So I want to down convert them by different frequency reference signals. Is it possible using DDS core from Xilinx core generator?
Any ideas...thanks