How can i generate a Pulse with a time = 35 ns

[yasser_shoukry]

I need an RTL code in verilog or VHDL to generate a pulse with high time = 10 us ?
How can i meet this timing constraint?

Thanks in advance

 

[echo47]

What frequency is your clock?
What triggers the pulse? Is the trigger synchronous to the clock?
What type of FPGA/CPLD are you using?

One simple solution could be to use a 200 MHz clock, and count seven cycles.

 

[yasser_shoukry]

I am using the Spartan3 starter kit, it has a built in 50 MHz crystal. This module should be triggered when 1 is written to its control register

Added after 2 minutes:

Sorry i have written the high time in my first post 35 nsec while the correct is 10 usec

 

[echo47]

You can generate 10us by counting 500 clocks at 50MHz.
I don't quite understand your control register, but maybe you can use this module.
Comment-out one of the two "count" assignments depending on your desired trigger type.

module top (clk, in, out);   // detect rising edge, generate 500-clock pulse
  input         clk, in;
  reg     [2:0] delay = 0;   // anti-metastability shift register
  wire          trigger = ~delay[2] & delay[1];   // detect rising edge
  reg     [9:0] count = 0;
  output        out;
  assign        out = count[9];

  always @ (posedge clk) begin
    delay <= {delay,in};
    count <= trigger ? -500 : count ? count + 1 : count;   // retriggerable
  //count <= count ? count + 1 : trigger ? -500 : count;   // non-retriggerable
  end
endmodule

 

[quy1001]

How about using a DCM.

 

[vijaiiyer]

Easiest method is to use a counter. Just count 500clocks to get the trigger... Decode to write the 1.