How can I convert .db to .v

[alerta]

When I used verdi to open a netlist .v,there is a lot of errors
i think maybe it's the problem that i didn't use the library
but i use the .db library,the problem still exist
so i want to covert the library .db to .v
how can i do this?
thanks

 

[shankarmit]

use DC and load the DB and then try to write out a netlist.. hope this works out

Regards
Shankar

 

[semi_jl]

You need the std-cell information, I think.

 

[dcreddy1980]

Hi,

i want to covert the library .db to .v

Say "test" is the name of your library and then load the below two commands in to your DC :

read_db test.db
write -format verilog -out test

Regards,
dcreddy

 

[xiexie57]

But you need,org all db about it
TRY
read test.db
write -format verilog -out test.v

 

[ravurig]

I think ur problem is not to convert .db to .v
but to access ur .db library in a proper way
check ur target library command

 

[sevid]

hi,all
when i input
"read test.db
write -format verilog -out test.v "
in my DC command line,it doesn't work,and an error appears:
current design is not defined.
DC realize ur test.db a library file ,but not a design.
How to convert it ,pls tell me.

Thanks in advance.
sevid

 

[jiang]

after reading your all hdl files,
you should use "current_design" command to set your top module.

current_design your_top_module

 

[rameshsuthapalli]

Hi,

I think DC cont give the library information in verilog format.
I think if u try using the librariy compiler for the above requirement but i am not sure about that.

Regards.
Ramesh.S

 

[sevid]

hi, alerta
With the help of VSS,as far as i know,u can convert ur .db library file,used when u synthesizing ur design,to .hdl library file for ur simulation.
So justifiably,i think u can translate ur .db into .v with the help of VCS.
Regards
sevid