windtutelary
Newbie level 2
hi all,
i have a problem with VHDL and verilog mixed ,
now VHDL and verilog is connect success,
VHDL is TOP and VHDL has a shared variables,
how can I call a VHDL shared variables inside Verilog code???
Thank you
i have a problem with VHDL and verilog mixed ,
now VHDL and verilog is connect success,
VHDL is TOP and VHDL has a shared variables,
how can I call a VHDL shared variables inside Verilog code???
Thank you