how can high voltage MOSFETS protect itself against ESD?

[mengcy]

ldmos esd

A thick gate oxide process provides 16V Vgs and Vds LDMOS mosfets.
How can it protect itself without additional ESD devices,like GGNMOS or GGPMOS?

Does it need special layout rules or just following the usual rules?

 

[erikl]

how to protect mosfets

Does it need special layout rules or just following the usual rules?

It needs special layout rules:
- Minimum unsalicided width on P and N transistor source & drain
- both P+ & N+ guardRings

 

[DenisMark]

high voltage device

Usually LDMOSes show non-uniform triggering and related weak ESD behavior ever if there gate or body triggering techniques are used. The best starting point is to contact with ESD designers on FAB to get advices and TLP plots.
The risk of ESD fail is high enough with selfprotected LDMOS.

 

[tlihu]

high voltage esd

Are there any references or resources concerning this topic?

 

[ESDSolutions]

hv esd layout

DenisMark is right. Many High voltage NMOS devices have serious issues with uniform triggering within multifinger devices as well as single finger!

This problem is most visible when multiple pulses are used during the ESD stress at the same level. E.g. A foundry can claim self protection capabilities reaching 4kV HBM but it is possible that by stressing the device multiple times at 2kV that it will fail. You should certainly ask for information about 'repetitive stress' tests. I would not trust a HV MOS device protection claim without such information!

It is probably better to provide a parallel protection clamp

Some references:
M. Mergens et al, “Analysis of lateral DMOS devices under ESD stress
conditions”, IEEE TED, Nov 2000, pp. 2128

B. Keppens et al, "ESD Protection Solutions for High Voltage Technologies", EOS/ESD symposium 2004

B. Keppens et al., “Contributions to Standardization of Transmission
Line Pulse Testing Methodology”, Proc. EOS/ESD 2001, pp. 461-467.

 

[mengcy]

how to protect from high voltage?

thanks very much.
ESDSolutions,where can I download the
"ESD Protection Solutions for High Voltage Technologies"

 

[ESDSolutions]

esd protect hv ldmos

I believe that you can download the paper from the website of Sarnoff Europe at
**broken link removed**

It may be that you need to register before you can download the document.

Let me know if you need further help.

ES

 

[timof]

hv device esd

Many High voltage NMOS devices have serious issues with uniform triggering within multifinger devices as well as single finger!

Could anyone provide some insight into the problem of non-uniform triggering in ESD devices?

Are the root causes for non-uniform triggering in ESD device well known?
Is this effect (non-uniformity) related to metal layouts? Wirebond location for source/drain? Wirebond location for gate? Or is this non-uniformity a random effect (random either form device to device, or for repetitive tests)?

Have there been some papers on simulation of these effects? Any references?

M.