kickbeer
Full Member level 3
As in most of the other designs of the latches, there is always a biasing transistor
connected to the source of the NMOS in the regenerative loop. In that architecture, the biasing transistor is eliminated and self biasing techniques are used to attain required voltage levels and therefore rail to rail output is closely achieved. How a self-biasing circuit is actually accomplished?
Thx in advanced
connected to the source of the NMOS in the regenerative loop. In that architecture, the biasing transistor is eliminated and self biasing techniques are used to attain required voltage levels and therefore rail to rail output is closely achieved. How a self-biasing circuit is actually accomplished?
Thx in advanced