Hold Delay Buffer Circuit

[kumar_eee]

When we have Hold violation, we usually add the delay buffers at the endpoint.

The hold delay buffer is nothing but 2 inverter connected in series.

In that, which inverter is under-driven inverter? Is the first-level inverter or the second-level inverter?

 

[bschaitanya]

kumar,

It's not necessary to add the delay or normal(ie.. utilization not an issue) buffer at the endpoint. we can do that (adding at endpoint) if there is a margin otherwise we look for diverging point we keep buffer by checking required margin there are not.

But I dont understand "hold delay buffer is nothing but the back-to-back inverter connected".. can you explain..

 

[oratie]

Usually, the hold delay buffers contains 4 inverters (may contains more), the first level and the last level inverters are the same as in usual buffer (non-delay). But, the middle inverters gives the real delay - they have bigger channel length (as an example). Such delay cells provide huge delay. If you need a small delay to add, the tool may use simple buffers (2 inverters) (because, it also has some internal delay).