HighSpeed Clock Subsystem Design

[Sigma|Six]

Hi All, I need to build a new HighSpeed Clock subsystem.
It should run at 800MHz to 1Ghz
Other than jitters, what are the characteristic that I should aware of?

Any good reference/books?

:?::?:

 

[tom_hanks]

HI,
look for delay, EMI and bounces on near by nets...

best of luck

 

[rfmw]

Grand Daddy's bible for high-speed is Motorola's (now ONSemi's) MECL System Design Handbook HB205/D:

https://www.onsemi.com/pub/Collateral/HB205-D.PDF


Then I suggest you to take a look at Howard Johnson's both "Black Magic" books, Eric Bogatin's Signal Integrity Simplified, and a couple more...


Edit: sorry, seems that I somehow overlooked your subject. These book are good for high-speed-PCB design on a board level, not chip level.

 

[Sigma|Six]

hi rfmw, it's a system level design, not chip level.
your advice are appreciated.

I am studying a design where the design uses PLL chips to synthesize the clock in PECL.

Distribute all the clock in PECL.
and ultimately change it to ttl level.

Since it is ultimately changed into TTL level for the electronics system, is there any specific reason why I need to distribute it in PECL's form ?

Also, I have an idea to replace all the micrel-synergy chipset using FPGA. e.g Altera's PLL or Xilinx DCM. is that a good idea? or a separate chipset is better ?

Added after 1 minutes:

hi rfmw, it's a system level design, not chip level.
your advice are appreciated.

I am studying a design where the design uses PLL chips to synthesize the clock in PECL.

Distribute all the clock in PECL.
and ultimately change it to ttl level.

Since it is ultimately changed into TTL level for the electronics system, is there any specific reason why I need to distribute it in PECL's form ?

Also, I have an idea to replace all the micrel-synergy chipset using FPGA. e.g Altera's PLL or Xilinx DCM. is that a good idea? or a separate chipset is better ?