buenos
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hi
Intel says, put all high speed nets (DDR, IDE, PCI, USB) into inner layers, and make them to be striplines. I think its good, but is it necessary?
If i use a not intel, and not GHz processor (500MHz, AMD-GeodeLX embedded uP), but i use the same interfaces, (DDR, IDE, PCI, USB) then should i put them inner? If i do that, my layer count starts at 8 layers. The AMD says, we can develop 4-6 layer PCBs for that uP, it means, there are high speed buses on outer layers.
So, who has wright?
Both of them would pass the FCC?
Another aspect: there are Wlan and bluetooth modules connected to the motherboard.
Intel says, put all high speed nets (DDR, IDE, PCI, USB) into inner layers, and make them to be striplines. I think its good, but is it necessary?
If i use a not intel, and not GHz processor (500MHz, AMD-GeodeLX embedded uP), but i use the same interfaces, (DDR, IDE, PCI, USB) then should i put them inner? If i do that, my layer count starts at 8 layers. The AMD says, we can develop 4-6 layer PCBs for that uP, it means, there are high speed buses on outer layers.
So, who has wright?
Both of them would pass the FCC?
Another aspect: there are Wlan and bluetooth modules connected to the motherboard.