Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Hi...is there any one working in cadence RTL compiler

Status
Not open for further replies.

srini.pes

Member level 3
Joined
May 28, 2010
Messages
61
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,288
Location
NIT calicut
Activity points
1,725
Respected all
If you are working in the cadence RTL compiler domain
please let me know
i will contact you and i wil clarify my doubts regarding timing analysis
please help me
 

Respected all
If you are working in the cadence RTL compiler domain
please let me know
i will contact you and i wil clarify my doubts regarding timing analysis
please help me

What doubts u have?
 

What doubts u have?

Hi ....
Actually am having a negative slack og -14000 ps for a clock of 10 ns...
i have used synthesize -to_mapped -effort high -incr

slack reduced to -9000 ps....
i need to reduce it to a small positive value
can u suggest me some models
 

You must redesign your sdc constraint file or/and set you hdl code to meet the timing requirements through the better performance design and the technology you are using can limit your design to a higher or lower clock frequency. Remember the tradeoffs: area, timing, power. As you are reducing the area, with the same clock. More power is required for example.
 

Did you analyze first why its failing by that much large negative slack? what kind of path is it ? I2C or C2C or I2O path etc? You need to then look at the path and see if some constraints are missing ...Dont expect the tool to solve everything especially if its failing by more 30-40% of the clock period... This applies to all synthesis tools irrespective of vendor..also check how many paths are failing and whats the histogram looks like ? Is it only few paths or may be a 100 paths etc and if it is handful , then do all they have common start/end point or is it from register bank or macro paths or paths from one block to another ...check if there are any full/half adders, large multiplexers that can decomposed or huge fanout or any blocks/sub designs where preserve attr is set etc...For STA, analysis is key ..once you analyze and describe the problem more detailed, you will get more precise answers, else answers will be very generic and you will still be clueless...Good luck.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top