jdyrholm
Newbie level 2
cmos op amp design
I have a question concerning the design of CMOS Op Amp in Spice. My professor gave us this project 2 weeks before the end of the semester, and I am stressed with this and studying.
Anywho....how should I begin with the following specs:
VDD = -Vss = 3.00 V
Av > 5000
Phase Margin = 40-60-degrees
Unity Gain Bandwidth > 5 MHz
SR > 10 V/micro-s for a CL of 10 pF
-1.0 V ≤ Input Common Mode Range ≤2.0 V
Output Voltage Range of ±1.7 V
Number of active devices <18
Total resistors value not to exceed 100kΩ
Channel length of all devices = 0.8 micro
It has to be simulated with Spice
Thanks!
I have a question concerning the design of CMOS Op Amp in Spice. My professor gave us this project 2 weeks before the end of the semester, and I am stressed with this and studying.
Anywho....how should I begin with the following specs:
VDD = -Vss = 3.00 V
Av > 5000
Phase Margin = 40-60-degrees
Unity Gain Bandwidth > 5 MHz
SR > 10 V/micro-s for a CL of 10 pF
-1.0 V ≤ Input Common Mode Range ≤2.0 V
Output Voltage Range of ±1.7 V
Number of active devices <18
Total resistors value not to exceed 100kΩ
Channel length of all devices = 0.8 micro
It has to be simulated with Spice
Thanks!