[help] what's wrong with this circuit?

[8k-rom]

In this circuit ,I want to get Y=0 when IN=1&clk=1.
CLK is a pulse with PW=20ns ,
At the begining,signal IN is low(IN=0),and Y=1 ,so M1 M2 off, M3~M6 on.
When signal IN convert to high(1),and Y=0 ,so M1 M2 on,M3~M6 off. In this case ,IN and CLK was disconnected, and the input terminals of nand are high,so Y=0.


But after simulation by hspice ,the outcome is not perfect at all..
I don't konw why? who can give me some tips??

 

[red_boy]

When Y is high, all of switchs are open. IN and clk can not be transfered by switched. So the state of circuit is locked.

 

[8k-rom]

When Y is high, all of switchs are open. IN and clk can not be transfered by switched. So the state of circuit is locked.

I'm sorry.I have not figured out your meaning.
Tell me more details plz...

when y=1,just M3...M6 are on,and M1,2 are off ...then why in and clk cannot be translated by switch...?

 

[Fom]

In this case ,IN and CLK was disconnected, and the input terminals of nand are high,so Y=0.

They are not disconnected. You have a diode from drain to source.
Change Nwell connection of PMOSl to VDD instead of source.

 

[8k-rom]

In this case ,IN and CLK was disconnected, and the input terminals of nand are high,so Y=0.

They are not disconnected. You have a diode from drain to source.
Change Nwell connection of PMOSl to VDD instead of source.

Thx....It is ok now!
I had never considered the difference between these two connections.