help verilog hdl program

[hareshcooleng]

error-For statement is only supported when the stop test condition is a comparison between the loop variable and a constant.
any one know how i solve that.


module top(n, result);
input [3:0] n;
output [31:0] result;
reg [31:0] result;
always @
begin
result=factorial;
end


function [31:0] factorial;
input [3:0] num;
reg [3:0]index;
begin
factorial=num ?1:0;
for(index=2; index<=num; index=index+1 )
factorial=index * factorial;
end
endfunction
endmodule

 

[FvM]

There are two issues with your code. The first one is a formal syntax problem, that can be easily overcome by rewriting the loop:

for(index=2; index<=15; index=index+1) // index > 12 causes result overflow
  if (index<=num)
    factorial=index * factorial;

The second and more basic problem reveals, if you try to synthesize the suggested code. I guess, that you didn't think yet about the nature of a for loop iteration in Verilog. It's not the same as a loop in a sequential programming language, it's a direction to build parallel logic. Unfortunately the parallelization can easily break up all reasonable resource limits. You should limit index to 12 to keep the 32 bit result range.