vijayanand_ME
Member level 1
Hi,
We have a processor which can support SS7 signaling and
I have captured some packets from the processor and following are the details
First packet FF FF 01 03 BC D4
second packet FF FF 01 00 27 E6
BC D4 are the CRC -16 field in the first packet and
27 E6 are the CRC-16 field in the second packet.
From the Processor data sheet i found "16-bit CRC-CCITT" is used for generating CRC.
If i calculate the CRC from the online tools i am not getting the right CRC (compare to my packets)
Can any one help me how to get this CRC and I am implementing this in FPGA (Verilog or VHDL)
Calulation steps are welcome for easy understanding..
With Regards,
Vijay
We have a processor which can support SS7 signaling and
I have captured some packets from the processor and following are the details
First packet FF FF 01 03 BC D4
second packet FF FF 01 00 27 E6
BC D4 are the CRC -16 field in the first packet and
27 E6 are the CRC-16 field in the second packet.
From the Processor data sheet i found "16-bit CRC-CCITT" is used for generating CRC.
If i calculate the CRC from the online tools i am not getting the right CRC (compare to my packets)
Can any one help me how to get this CRC and I am implementing this in FPGA (Verilog or VHDL)
Calulation steps are welcome for easy understanding..
With Regards,
Vijay