Help require on verilog

[PekingBoy]

Hi,i got a verilog file as the follow,

...
case(f4Cnt)
'd0:
begin
a <= b+1;
f4Cnt <= f4Cnt+1;
end
'd1:
begin
a <= b+1;
f4Cnt <= f4Cnt+1;
end
'd2,
'd3,
'd4,
'd5:
begin
a <= c+1;
f4Cnt <= f4Cnt+1;
end
default:
begin
a <= 'd0;
f4Cnt <= 'd0;
end
endcase
...
The question is what the operation will be in state 'd2,'d3,'d4?

Thanks in advance.

 

[kungfu007]

case(f4Cnt)
'd0:
begin
a <= b+1;
f4Cnt <= f4Cnt+1;
end
'd1:
begin
a <= b+1;
f4Cnt <= f4Cnt+1;
end
'd2,
'd3,
'd4,
'd5:
begin
a <= c+1;
f4Cnt <= f4Cnt+1;
end
default:
begin
a <= 'd0;
f4Cnt <= 'd0;
end
endcase
...
The question is what the operation will be in state 'd2,'d3,'d4?

After `d1 state, then the state will be in state `d2 -> `d3 -> `d4.

Am i answer your questioN?

 

[deepu_s_s]

Hi ,

I think there is no operation done . U are just adding 3 cycles of delay

 

[farhantariq]

...
case(f4Cnt)
'd0:
begin
a <= b+1;
f4Cnt <= f4Cnt+1;
end
'd1:
begin
a <= b+1;
f4Cnt <= f4Cnt+1;
end
'd2,
'd3,
'd4,
'd5:
begin
a <= c+1;
f4Cnt <= f4Cnt+1;
end
default:
begin
a <= 'd0;
f4Cnt <= 'd0;
end
endcase
...
The question is what the operation will be in state 'd2,'d3,'d4?

Be a little more Precise.

At the moment it looks like a 3 cycle delay. Nothing else

 

[icelucent]

That means the state of 'd2 'd3 'd4 'd5 are the same state.

 

[PekingBoy]

That means the state of 'd2 'd3 'd4 'd5 are the same state.

Thank you,everyone.
I think icelucent is right.

 

[FvM]

The logic behaviour can be unequivocally concluded from Verilog language specification. The 2 to 5 are not the same state, in so far as they are cycled sequentially, they are just handled by the same case expression. This doesn't necessarily mean much for the synthesis tool, that can be expected to treat each case independently when minimizing the logic.

The unsized 'd2 constant can be written simply 2, by the way.