jianhuachews
Member level 2
Hi guys, I've just started learning VHDL for a week on my own so i'm still very new to it. I'm doing a practice on implementing a 4-bit parallel-out serial shift register.. My codings can be complied but it shows
" # ** Fatal: (vsim-3347) Port 'din' is not constrained.
# Time: 0 ns Iteration: 0 Instance: /shiftreg File: /EDCP6/proj15/jianhua/vhdl/Lab3_compare.vhd Line: 5
# FATAL ERROR while loading design " when i tried to simulate it. can anyone help me out with this?
***********************************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity shiftreg is port (
din: in std_logic_vector; -- data in
clk: in std_logic; -- Clock
clr: in std_logic; -- Clear
pset: in std_logic; --Preset
q : out std_logic_vector(3 downto 0) -- output Q
);
end;
architecture rtl of shiftreg is
begin
process (clk, clr,pset)
begin
if (pset='0') then
q <= "1111";
elsif (clr='0') then
q <= "0000";
elsif (clk'event and clk = '1') then
q <= din;
end if;
end process;
end rtl;
" # ** Fatal: (vsim-3347) Port 'din' is not constrained.
# Time: 0 ns Iteration: 0 Instance: /shiftreg File: /EDCP6/proj15/jianhua/vhdl/Lab3_compare.vhd Line: 5
# FATAL ERROR while loading design " when i tried to simulate it. can anyone help me out with this?
***********************************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity shiftreg is port (
din: in std_logic_vector; -- data in
clk: in std_logic; -- Clock
clr: in std_logic; -- Clear
pset: in std_logic; --Preset
q : out std_logic_vector(3 downto 0) -- output Q
);
end;
architecture rtl of shiftreg is
begin
process (clk, clr,pset)
begin
if (pset='0') then
q <= "1111";
elsif (clr='0') then
q <= "0000";
elsif (clk'event and clk = '1') then
q <= din;
end if;
end process;
end rtl;