akhileshchidare
Member level 3
lan9115
Hello,
I have a problem with DMA burst transfers when communication is between Cyclone 2 FPGA nad SMSC LAN 9115.
I have a common bus sharing for SRAM and LAN 9115.
The problem is that ,when i get an interrupt from the LAN device i read the data from LAN FIFO and put in a temporary buffer.when i print the temporary buffer i see that most of the received data is corrupted.The problem is with only DMA.
when i dont use DMA i get everything right and i am able to process the data properly.
I thought the problem is with DMA.So i transferred data from one block of SRAM to other its working fine.
when i searched in the altera website i found an errata saying the following
The LAN91C111 component does not use the ARDY signal and therefore may not properly handle bursts from peripherals such as a direct memory access (DMA) controller.
Workaround: Do not use bursting peripherals such as DMA with the LAN91C111 component.
Has any one faced such issues before with Cyclone 2 FPGA and NIOS IDE.
Did the altera resolved the issues in the later versions?
Thanks !!!
Akhilesh Chidare
Hello,
I have a problem with DMA burst transfers when communication is between Cyclone 2 FPGA nad SMSC LAN 9115.
I have a common bus sharing for SRAM and LAN 9115.
The problem is that ,when i get an interrupt from the LAN device i read the data from LAN FIFO and put in a temporary buffer.when i print the temporary buffer i see that most of the received data is corrupted.The problem is with only DMA.
when i dont use DMA i get everything right and i am able to process the data properly.
I thought the problem is with DMA.So i transferred data from one block of SRAM to other its working fine.
when i searched in the altera website i found an errata saying the following
The LAN91C111 component does not use the ARDY signal and therefore may not properly handle bursts from peripherals such as a direct memory access (DMA) controller.
Workaround: Do not use bursting peripherals such as DMA with the LAN91C111 component.
Has any one faced such issues before with Cyclone 2 FPGA and NIOS IDE.
Did the altera resolved the issues in the later versions?
Thanks !!!
Akhilesh Chidare
