ethan
Member level 3
Hi everybody,
I have posted this message on "Analog Circuit Desig Board". But no replied so far. Can anyone give some instruction on this? Thank you.
I am a student and right now want to duplicate a OPAMP design from a IEEE journal for a project. The schematic (bmp file) is attached in this post (sorry I don't know how to directly post it, so I use the attachment).
Since I have no so much experience, I need your help to interprete this design. First I want to briefly introduce this amplifier before I go into it.
They used this opamp to sense substrate noise with one input connecting the substrate through big MOS cap and another input connecting the quiet ground. The previous design (from another group) used 0.5 micron technology with 3.0 v supply, consuming 100mw. The current IEEE paper design used 0.35 micron technology. These two schematics were indentical. I have made some comments based on my understood and list as following. Please feel free to comment them and give me some advise. I am also use 0.35 micron and 3.3v power supply.
1. Those two groups demonstrated it is wideband amplifier and have bandwidth from 100KHz to 1GHz. The reason why it is wideband, I think this is current mode amplifier, since its input impedance is low (1/gm5 or 1/gm7) and also its ouput impedance is also low (1/gm10=50ohms, or 1/gm11). But, if it is current mode amplifier, it should sense current input, but apparently that big MOS cap sense substrate noise voltage, no noise current, Why? Maybe I am wrong.
2.Biasing part:
I have set the M9 branch and M8 branch 20uA each, and M14 branch 10uA since I think M14 branch is only used for biasing the gated of M5 and M7. I know there is feedback between M13 and M14, and both M13 and M14 use to bias the gates of M5 and M7. But I don't know how to interpret it and feel hard to set the node voltage of gate of M14.
How large the DC voltage of the gates of M5, M7 and M14 should I get? Right now I set it at 1.8-2.0v in between to let two PMOS M8 and M9 (current mirror) with the same Vds. AM I right?
3. Power-Consumption:
In the previous paper (0.5 micron, 3.0 v supply, 100mw, then current in total will be 33.3mA), but if we look at the output stage (since it should match the 50ohms probe), the 1/gm10 or 1/gm11 should be 50 ohms also, then the total impedance of branch M10 or M11 with probe connected will be 100ohms. Then only the output stage will consume 3.0v/100ohms=30mA, which is almost 33.3mA ???
So, if I set M3 branch with 40uA and others are 20uA each except output stages, is that doable?
4. Vdd-Gnd and Input stage:
If I use 0.35 um technology with 3.3 v power supply, can I set Vdd=3.3 v and Vss=0 v, or Vdd=1.65 v and Vss=-1.65v? Right now, I choose the previous case, since this is related to the input stage biasing and I thought I should set certain voltage at the gates of M1 and M2 in order to let the M1 and M2 and also M3 in saturation. Right now, I set the gate voltages of M1 and M2 at 1.5-2.5v in between (not nailed it yet). Can I ?
5. Resistor loads:
I thought why they picked resistors as load, there are two reasons. One is that they don't want to achieve high gain with relativey low output impedance of the first stage. As they demonstrated in their papers, it only has 3dB gain from 100kHz to 1 Ghz. The second reason is that there is no parasitic capacitance instead of MOSFET load, then they can push the pole to the hight frequency to achieve high bandwidth. Am I right? What's the principle with design of resistor load?
6. Output stage:
How can I choose the MOSFET of the source follower of output stage? Just calculate to achieve 1/gm=50 ohms?
I appreciate your comments and help.
Good weekend.
ethan
I have posted this message on "Analog Circuit Desig Board". But no replied so far. Can anyone give some instruction on this? Thank you.
I am a student and right now want to duplicate a OPAMP design from a IEEE journal for a project. The schematic (bmp file) is attached in this post (sorry I don't know how to directly post it, so I use the attachment).
Since I have no so much experience, I need your help to interprete this design. First I want to briefly introduce this amplifier before I go into it.
They used this opamp to sense substrate noise with one input connecting the substrate through big MOS cap and another input connecting the quiet ground. The previous design (from another group) used 0.5 micron technology with 3.0 v supply, consuming 100mw. The current IEEE paper design used 0.35 micron technology. These two schematics were indentical. I have made some comments based on my understood and list as following. Please feel free to comment them and give me some advise. I am also use 0.35 micron and 3.3v power supply.
1. Those two groups demonstrated it is wideband amplifier and have bandwidth from 100KHz to 1GHz. The reason why it is wideband, I think this is current mode amplifier, since its input impedance is low (1/gm5 or 1/gm7) and also its ouput impedance is also low (1/gm10=50ohms, or 1/gm11). But, if it is current mode amplifier, it should sense current input, but apparently that big MOS cap sense substrate noise voltage, no noise current, Why? Maybe I am wrong.
2.Biasing part:
I have set the M9 branch and M8 branch 20uA each, and M14 branch 10uA since I think M14 branch is only used for biasing the gated of M5 and M7. I know there is feedback between M13 and M14, and both M13 and M14 use to bias the gates of M5 and M7. But I don't know how to interpret it and feel hard to set the node voltage of gate of M14.
How large the DC voltage of the gates of M5, M7 and M14 should I get? Right now I set it at 1.8-2.0v in between to let two PMOS M8 and M9 (current mirror) with the same Vds. AM I right?
3. Power-Consumption:
In the previous paper (0.5 micron, 3.0 v supply, 100mw, then current in total will be 33.3mA), but if we look at the output stage (since it should match the 50ohms probe), the 1/gm10 or 1/gm11 should be 50 ohms also, then the total impedance of branch M10 or M11 with probe connected will be 100ohms. Then only the output stage will consume 3.0v/100ohms=30mA, which is almost 33.3mA ???
So, if I set M3 branch with 40uA and others are 20uA each except output stages, is that doable?
4. Vdd-Gnd and Input stage:
If I use 0.35 um technology with 3.3 v power supply, can I set Vdd=3.3 v and Vss=0 v, or Vdd=1.65 v and Vss=-1.65v? Right now, I choose the previous case, since this is related to the input stage biasing and I thought I should set certain voltage at the gates of M1 and M2 in order to let the M1 and M2 and also M3 in saturation. Right now, I set the gate voltages of M1 and M2 at 1.5-2.5v in between (not nailed it yet). Can I ?
5. Resistor loads:
I thought why they picked resistors as load, there are two reasons. One is that they don't want to achieve high gain with relativey low output impedance of the first stage. As they demonstrated in their papers, it only has 3dB gain from 100kHz to 1 Ghz. The second reason is that there is no parasitic capacitance instead of MOSFET load, then they can push the pole to the hight frequency to achieve high bandwidth. Am I right? What's the principle with design of resistor load?
6. Output stage:
How can I choose the MOSFET of the source follower of output stage? Just calculate to achieve 1/gm=50 ohms?
I appreciate your comments and help.
Good weekend.
ethan
