Help me to build master oscillator

[skg]

Hi all,

I am very new to the world of CPLD/FPGA and VHDL. For my project, I want to generate 4 clock frequencies (20 MHz 2 nos and 40 MHz 2 nos) from a reference tcxo of 80 MHz. All the four output channels need to be phase matched with each other and with reference tcxo. Also the output clocks need to be low phase noise (better than -100dBc/Hz @1KHz offset). My tcxo is sine wave of 10 dBm power (2 Vp-p) has phase noise of -110 dBc/Hz@1KHz. 20 MHz output channels should be 1Vp-p (drive synthesizer) and 40 MHz is 5Vp-p (drive another microcontroller). This scheme needs to be implemented in cpld/fpga using verilog/vhdl. Any suggestion is appreciable. Please provide schematic and code if possible.
Thanks in advance.

SKG

 

[TrickyDicky]

What specific problems have you had so far?

 

[153rd]

The easiest way to 'create' different clocks is to use a counter.
Would be something like:
if (x < xxxx) then x <= X +1
if x = xxxx then CLK_out <= '1'; end if;
end if; Where X would be an integer, and CLK_out one of your clock outputs.

 

[lucbra]

The requirements are more related to analog than to digital design. Have you thought about how an FPGA/CPLD could match with your requirements?
Could a clock synthesizer do the job for you?