Help me the holdtime problem

[jjftt]

In a flip flop like this,anyone can tell me how is the hold time violation come from?
when clk=1,the first tran_mos is off, how can the input D effect the output Q?

 

[lakshman.ar]

can u pls put hte diagram bit more clearly ...
so that its easy to understand !!!

 

[tdminion]

suppose the clk changes at the 2nd transistor before the clk at the 1st transistor (they will not change simultaneously). Also, suppose the D input changes just before clk->1.

 

[jjftt]

sorry, i have redrawn the diagram.
when the clk=0, input d is stored in the first inverter loop. it need some time to go to stable before the clk=1, this is the setup time.
But how about the holdtime? when the clk=1,the first tran_cmos is turned off, why the input data d shoud be stable after the clk=1.

 

[lubee]

"But how about the holdtime? when the clk=1,the first tran_cmos is turned off, why the input data d shoud be stable after the clk=1."
I suppose that this is because of the propagation time that is required by the following combinational logic circuit.