trurl
Junior Member level 2
Hi All,
Could anyone explain why the following does not synthesize?
I'd like to count how many times an input signal has changed.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity test is
Port ( a : in STD_LOGIC );
end test;
architecture test of test is
begin
process(a)
variable counter : integer := 0;
begin
if (a'event) then
counter := counter + 1;
end if;
end process;
end test;
I get the following error:
ERROR:Xst:797 - ".../test.vhd" line...: unsupported Clock statement.
Best regards.
Could anyone explain why the following does not synthesize?
I'd like to count how many times an input signal has changed.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity test is
Port ( a : in STD_LOGIC );
end test;
architecture test of test is
begin
process(a)
variable counter : integer := 0;
begin
if (a'event) then
counter := counter + 1;
end if;
end process;
end test;
I get the following error:
ERROR:Xst:797 - ".../test.vhd" line...: unsupported Clock statement.
Best regards.