Help me modify divide by 2 counter code to divide by 4 counter

[anoop12]

Hi All,

I have written code for divide by 2 counter. I have to modify it for divide by
4 counter.
Does anyone knows how to modify it?
Any other way?

Thanks

Here is the code
---------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity divide_by_2 is
port (
clk_i : in std_logic;
reset : in std_logic;
clk_div2 : out std_logic

);
end divide_by_2 ;

architecture rtl of divide_by_2 is
signal q : std_logic;
begin
process(clk_i,reset)
begin
if (reset = '0') then
q <= '0';

elsif (clk_i'event and clk_i = '1') then
q <= not (q);

end if;
end process ;
clk_div2 <= q;

end rtl;

-----------------------------------------

 

[altair_06]

divide by four counter

Hi,

Use a counter to count two clock cycles and then invert the output.
Hope u got an idea.

 

[addn]

divide by 2 counter

signal q : std_logic_vector(1 downto 0);
................

begin
process(clk_i,reset)
begin
if (reset = '0') then
q <="00";

elsif (clk_i'event and clk_i = '1') then
q <=q+1;

end if;
end process ;

clk_div2 <= q(0);
clk_div4 <= q(1);

 

[karthikpnair]

what is divide by 4 counter

it would be better to hav the argument in the if loop of
addn's program as follows:

if ((reset = '0')or(q='00')) then
....................
..................

 

[Iouri]

divide by 4 ckt

Why do you need to add OP q ='00'??

 

[smileysam]

design of a divide by 4 counter

if u give output of one counter as clk to another i think ur prob will be solved!
in this case the the ckt will be asynchronous.

else

use a variable initially make it 0;
AT q <= not (q); var=var+1;

AT clk_div2 <= q; check if var is 2 then invert the clk_div2(have to make it bi-directional)
make var =0; again

If iam wrong please correct me guys!