Help me design a filter for a PLL with 125 MHz reference freq. and 2GHz output freq.

[sastry]

i have to design a pll with following specifications
i am using simulink

the reference frequency is 125 Mhz
the output frequency is 2.0 Ghz

how do i design the filter for the circuit
and the vco has 2 specifications in pll
the quiescent frequency and input sensitivity
now how can i calculate those.....
i have built the phase detector.how to i build the charge pump and the frequency divider.

 

[satyasiva]

pll specifications

u can use a digitsl counter for frequency divider as the division ratio is 16. (2x2x2x2).

 

[Tony Teng]

pll specifications

it's such a big system
hard to say

 

[RFDave]

Re: pll specifications

Have you looked at the Matlab central web page? There is an analog modeling seminar that goes into this in details. I've mentioned this a couple of times before, so if you search for my postings here, you'll find a link.


Dave
www.keystoneradio.com

 

[Meridian]

Re: pll specifications

i have to design a pll with following specifications
i am using simulink

the reference frequency is 125 Mhz
the output frequency is 2.0 Ghz

how do i design the filter for the circuit
and the vco has 2 specifications in pll
the quiescent frequency and input sensitivity
now how can i calculate those.....
i have built the phase detector.how to i build the charge pump and the frequency divider.

Try the 'PLL Tutorial' on this website: **broken link removed**

 

[yibinhsieh]

Re: pll specifications

For charge pump. there are many papers for mention this circuit.

For Divider, it is the critical part in the PLL design.

First of all, you can need to design the prescaler with dual modulus or single modulus.

For dual modulus prescaler, you can adopt 3/4 or 4/5. I usually use SCL or TSPC type. SCL means souce couple logic. TSPC means: true single phase clock.

After prescaler, the frequency is low, you can use asynchonus divider to control the dual modulus divider to achieve your divider number. The asynchous divider is CMOS type that it use many FFs and gates to implement it.

Yibin.

 

[rfzheng]

pll specifications

read book wrote Razavi about the PLL