Help for TTL to RSDS output timing HDL's coding

[chensanlien]

recently, i have a project about sending ttl signal to lcd source driver(rsds signal).

In this project, we decide to use altera cyclone (with rsds output I/O).

RSDS timing is request to send data @ raising (even data bits)
@ falling (odd data bits) edge clock,

so I coding this code for this specification, as following:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

-- DECLARE ENTITY
ENTITY RSDS_Receiver IS
PORT(
CLOCK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
RDATA_IN : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
GDATA_IN : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
BDATA_IN : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

RRSDS_OUT : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
GRSDS_OUT : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
BRSDS_OUT : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END RSDS_Receiver;

-- ARCHITECTURE SECTION
ARCHITECTURE BEHAVIOR OF RSDS_Receiver IS

-- DEFINE STATE MACHINE
TYPE STATE_TYPE IS (RESET, ODD, EVEN);

-- DECLARE PRESENT & NEXT STATE SIGNAL
SIGNAL PRESENT_STATE, NEXT_STATE : STATE_TYPE;

BEGIN

--[1] ASYNCHRONOUS RESET
RESET_REGROCESS(CLOCK_IN, RESET_IN)
BEGIN
IF RESET_IN = '1' THEN
PRESENT_STATE <= RESET;
ELSIF RISING_EDGE (CLOCK_IN) THEN
PRESENT_STATE <= NEXT_STATE;
END IF;
END PROCESS;

--[2] STATE & DATA OUTPUT PROCESS
PROCESS(PRESENT_STATE, CLOCK_IN)
BEGIN
--SETUP DEFAULT OUTPUT
RRSDS_OUT <= "ZZZZ";
GRSDS_OUT <= "ZZZZ";
BRSDS_OUT <= "ZZZZ";
--SETUP DEFAULT NEXT_STATE
NEXT_STATE <= RESET;

--SWITCH STATE MACHINE
CASE PRESENT_STATE IS
WHEN RESET =>
RRSDS_OUT <= "ZZZZ";
GRSDS_OUT <= "ZZZZ";
BRSDS_OUT <= "ZZZZ";

NEXT_STATE <= EVEN;

WHEN EVEN =>
IF CLOCK_IN = '1' THEN
RRSDS_OUT(0)<= RDATA_IN(0);
RRSDS_OUT(1)<= RDATA_IN(2);
RRSDS_OUT(2)<= RDATA_IN(4);
RRSDS_OUT(3)<= RDATA_IN(6);

GRSDS_OUT(0)<= GDATA_IN(0);
GRSDS_OUT(1)<= GDATA_IN(2);
GRSDS_OUT(2)<= GDATA_IN(4);
GRSDS_OUT(3)<= GDATA_IN(6);

BRSDS_OUT(0)<= BDATA_IN(0);
BRSDS_OUT(1)<= BDATA_IN(2);
BRSDS_OUT(2)<= BDATA_IN(4);
BRSDS_OUT(3)<= BDATA_IN(6);
END IF;
NEXT_STATE <= ODD;

WHEN ODD =>
IF CLOCK_IN = '1' THEN
RRSDS_OUT(0)<= RDATA_IN(1);
RRSDS_OUT(1)<= RDATA_IN(3);
RRSDS_OUT(2)<= RDATA_IN(5);
RRSDS_OUT(3)<= RDATA_IN(7);

GRSDS_OUT(0)<= GDATA_IN(1);
GRSDS_OUT(1)<= GDATA_IN(3);
GRSDS_OUT(2)<= GDATA_IN(5);
GRSDS_OUT(3)<= GDATA_IN(7);

BRSDS_OUT(0)<= BDATA_IN(1);
BRSDS_OUT(1)<= BDATA_IN(3);
BRSDS_OUT(2)<= BDATA_IN(5);
BRSDS_OUT(3)<= BDATA_IN(7);
END IF;
NEXT_STATE <= EVEN;
END CASE;
END PROCESS;
END BEHAVIOR;


After synthesis & simulation, we got a bad result (glitching).
Does any one can solve this problem ?

Sincerely,

 

[lovou]

try to change the

IF CLOCK_IN = '1' THEN

to if clock_in'event and clock_in='1'

in order to make it synchronous with the clock and it will change every clock peroid

not the glitch any more

greetings.