[help!] CMFB circuits

[qslazio]

In a simple two-stage single ended miller opamp with pmos input diff pair and current mirror load, what's the simplest continuous-time CMFB circuits to balance output CM voltge at 0.5VDD?
can anyone give me an example of this CMFB circuit?


BTW: Is it needed a CMFB circuits in a opamp used in closed loop configuration(like bandgap)?

Thanks very much!!

 

[ezt]

Hi.
If your opamp is single-ended, there's no need for CMFB. However, fro more information about CMFB circuits, you can refer to Dr. Razavi's ANALOG IC DESIGN or Dr. Gray's or Sr. Johns's. There are lots of sources.

Regards,
EZT

 

[qslazio]

thanks ezt!
i'm another question.
if there is no need for CMFB as single-ended op, how can we stable our output stage at 1/2VDD, rather than ~0V or ~VDDV, one of the nmos and pmos of output stage will be in linear region!!(suppose the output is a Common Source nmos with pmos current source for load)

 

[Btrend]

in 2-stage OP, there is a standard method to design it, u can check it some text book. if u follow that method, u will get a good bias point at the output. but it may not be exactly 0.5VDD. cause there is different ro in PMOS & NMOS. even though ur ro_PMOS=2*ro_NMOS, there is still "channel length modulation" effect, so it's hard to get rop=ron (i.e. 0.5VDD biased) at the output noe.

 

[kamalakkannan]

hi..
first of all,why do u need 0.5vdd at the output of single stage satge opamp.normallysingle ended opamp in openloop test,if u connect both input together.output will be surely in known bias state..not VDD or VSS.
i hope u are designing this opamp for closed loop only..once you put opamp ,opamp output voltage is decided by ur closed loop gain.
--\kamal