Help about verilog :((( urgent....

[damla61]

ı have to design 32 byte adder/subtractor ın verilog using carry look adder.. but I am not so good ın verilog. could you help me (((

 

[shitansh]

What you expect here, that some one will write code for you?

You must have show your work and then if you are facing any problem in that case some one will definitely be there to help you.

good luck.

 

[shitansh]

YOu can read this book
SYNTHESIS OF ARITHMETIC CIRCUITS FPGA, ASIC, and Embedded Systems

Generate a generic two level n-digit base-B carry-lookahead adder.

library ieee; use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
package mypackage is
constant s: natural := 4;
constant n_div_s: natural := 4;
constant n: natural := s * n_div_s;
constant B: natural := 10;
subtype digit is natural range 0 to B-1;
type digit_vector is array (natural range <>) of digit;
procedure dot_operation(g1, p1, g0, p0: in std_logic; signal gg, pp: out std_logic);
end mypackage;

package body mypackage is
procedure dot_operation(g1, p1, g0, p0: in std_logic; signal gg, pp: out std_logic) is
begin
gg <= g1 or (g0 and p1); pp <= p1 and p0;
end procedure;
end mypackage;


library ieee; use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
use work.mypackage.all;
entity carry is
port 
(generalized_g, generalized_p: in std_logic_vector(s-2 downto 0);
c_in: in std_logic;
c_out: out std_logic_vector(s-1 downto 1)
);
end carry;

architecture circuit of carry is
begin
iterative_step: for i in 1 to s-1 generate
c_out(i) <= generalized_g(i-1) or (generalized_p(i-1) and c_in);
end generate;
end circuit;

library ieee; use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
use work.mypackage.all;
entity dot is
port 
(g, p: in std_logic_vector(s-1 downto 0);
generalized_g, generalized_p: out std_logic_vector(s-1 downto 0)
);
end dot;

architecture behavior of dot is
signal a, b: std_logic_vector(s-1 downto 0);
begin
a(0) <= g(0); b(0) <= p(0);
iterative_step: for i in 1 to s-1 generate
dot_operation(g(i), p(i), a(i-1), b(i-1), a(i), b(i));
end generate;
generalized_g <= a; generalized_p <= b;
end behavior;


library ieee; use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
use work.mypackage.all;
entity cla_carry_chain is
port 
(g, p: in std_logic_vector(n-1 downto 0);
c_in: in std_logic;
c_out: out std_logic_vector(n downto 0)
);
end cla_carry_chain;

architecture circuit of cla_carry_chain is
component dot
port 
(g, p: in std_logic_vector(s-1 downto 0);
generalized_g, generalized_p: out std_logic_vector(s-1 downto 0)
);
end component;
component carry
port 
(generalized_g, generalized_p: in std_logic_vector(s-2 downto 0);
c_in: in std_logic;
c_out: out std_logic_vector(s-1 downto 1)
);
end component;
signal q: std_logic_vector(n downto 0);
signal gg, pp: std_logic_vector(n-1 downto 0);
signal ggg, ppp, generalized_ggg, generalized_ppp: std_logic_vector(n_div_s-1 downto 0);
signal qqq: std_logic_vector(n_div_s downto 1);
begin
dot_iteration: for i in 0 to n_div_s-1 generate
dot_instantiation: 
dot port map(g(i*s+s-1 downto i*s),p(i*s+s-1 downto i*s), gg(i*s+s-1 downto i*s),pp(i*s+s-1 downto i*s));
end generate;
input_connections: for i in 0 to n_div_s-1 generate ggg(i) <= gg(i*s+s-1); ppp(i) <= pp(i*s+s-1); end generate;

--(n_div_s)-bit carry chain:
generalized_ggg(0) <= ggg(0); generalized_ppp(0) <= ppp(0); 
cla_carry_chain_description: for i in 1 to n_div_s-1 generate 
qqq(i) <= generalized_ggg(i-1) or (generalized_ppp(i-1) and c_in);
dot_operation(ggg(i), ppp(i), generalized_ggg(i-1), generalized_ppp(i-1), generalized_ggg(i), generalized_ppp(i));
end generate;
qqq(n_div_s) <= generalized_ggg(n_div_s-1) or (generalized_ppp(n_div_s-1) and c_in);

output_connections: for i in 1 to s generate q(i*s) <= qqq(i); end generate;
q(0) <= c_in;
carry_iteration: for i in 0 to s-1 generate
carry_instantiation: 
carry port map(gg(i*s+s-2 downto i*s), pp(i*s+s-2 downto i*s), q(i*s), q(i*s+s-1 downto i*s+1)); 
end generate;
output_carries_iteration: for i in 0 to s**2 generate c_out(i) <= q(i); end generate;
end circuit;



library ieee; use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.mypackage.all;
entity example11_7 is
port
(x, y: in digit_vector(n-1 downto 0);
c_in: in std_logic;
z: out digit_vector(n-1 downto 0);
c_out: out std_logic
);
end example11_7;

architecture circuit of example11_7 is
component cla_carry_chain
port 
(g, p: in std_logic_vector(n-1 downto 0);
c_in: in std_logic;
c_out: out std_logic_vector(n downto 0)
);
end component;
signal p, g: std_logic_vector(n-1 downto 0);
signal q: std_logic_vector(n downto 0);
begin
--q(0) <= c_in;
iterative_step: for i in 0 to n-1 generate
p(i) <= '1' when x(i) + y(i) = B-1 else '0';
g(i) <= '1' when x(i) + y(i) > B-1 else'0';
z(i) <= (x(i) + y(i) + conv_integer(q(i))) mod B;
end generate;
cla_carry_chain_instantiation: cla_carry_chain port map(g, p, c_in, q);
c_out <= q(n);
end circuit;


library ieee; use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.mypackage.all;
entity test_example11_7 is end test_example11_7;

architecture test of test_example11_7 is
component example11_7
port
(x, y: in digit_vector(n-1 downto 0);
c_in: in std_logic;
z: out digit_vector(n-1 downto 0);
c_out: out std_logic
);
end component;

signal x, y: digit_vector(n-1 downto 0);
signal c_in: std_logic;
signal z: digit_vector(n-1 downto 0);
signal c_out: std_logic;
begin
device_under_test: example11_7 port map(x, y, c_in, z, c_out);

x <= (4,9,7,5,3,9,2,6,9,0,7,5,3,8,2,6), (4,9,7,5,3,9,2,6,9,0,7,5,3,8,2,6) after 10 ns;
y <= (0,9,2,4,6,1,7,3,0,9,3,4,6,1,7,3), (7,9,2,4,5,0,6,2,0,9,2,4,6,1,7,3) after 20 ns, 
(7,4,9,3,4,6,9,7,6,6,5,8,2,4,1,1) after 30 ns;
c_in <= '0', '1' after 15 ns;
end test;