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height of the standard cell in 40 nm and 90 nm technologies

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G.Satheesh Kumar

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hai all....


can anyone tell me the height of the standard cell in 40 nm and 90 nm technologies ???


thanQ
 

Hi Satheeth Kumar,

I worked on TSMC 40 nm it has standard cell height of 1.26 u and in 90nm i worked on CMOS90 which has standard cell height of 2.52 u. This is for single standard cell for double height standard cells it doubles.
 
For 90nm it was 2.61u
For the technologies we used 45nm,65nm has 1.2u
For 28nm it is 1.26u

For 45nm it has 1.4u..

please check with 65nm..

Guys, please give updates on 28nm, 22nm, etc
 

For 45nm it has 1.4u..

please check with 65nm..

Guys, please give updates on 28nm, 22nm, etc

It might vary from the company to company based on the technology you adopt.

Sorry, for 28nm technology I have mentioned wrongly, we have two adopted two technologies for 28nm :
One with 0.63u cell row height and other with 1.1u cellrow height.
 

Hi itsmeteja,

thanx for info..
 

The standard cell height is normally set up based on number of metal tracks. For example, you could design a 10-track standard cell library, which means that the height is 10 M1 track high. M1 track is minimum M1 width+spacing. For example, if your minimum metal pitch is 120nm (60nm wide metal, with 60nm spacing), the 10 track height would obviously be 120*10=1200nm or 1.2um. Now assuming you route the VDD/GND lines on the top and bottom metal track, you have about 8 M1 tracks free to route your wires and make contact to the transistor (VDD, GND, INPUTS and OUTPUTS). With Technology scaling, ideally you would want to keep the number of tracks the same, but since the M1 pitch scales every generation, you'd get a reduction in the standard cell height and essentially scaling in area.

So assuming you know the M1 pitch for a certain technology node (90nm or 40nm), and if you decide what the no of track height you want your standard cell to be, you can determine the height of the cell and figure out what it'll look at scaled nodes.
 

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