Elephantus
Junior Member level 3
lattice gsr
Hi all. I am debugging a design on Lattice ECP2 device, and during the PAR phase the ISPlever software generates a message similar to:
"Using <design net> as GSR".
Now, it is a bit odd to have a signal that should also be reset by GSR in the start, and which is actually a synchronous reset, connected to the global GSR net. The design is, of course, migrated from Xilinx and GSR is used throughout the design.
What I would like to have is a hardware-driven global-set-reset net, not driven by my logic.
Does anyone have any experience about this?
I would appreciate any help.
Hi all. I am debugging a design on Lattice ECP2 device, and during the PAR phase the ISPlever software generates a message similar to:
"Using <design net> as GSR".
Now, it is a bit odd to have a signal that should also be reset by GSR in the start, and which is actually a synchronous reset, connected to the global GSR net. The design is, of course, migrated from Xilinx and GSR is used throughout the design.
What I would like to have is a hardware-driven global-set-reset net, not driven by my logic.
Does anyone have any experience about this?
I would appreciate any help.