Glitches in AND gate with two inputs

[khaila]

supposed an AND gate with two inputs.
In practice there is supposed to be different delay on the inputs which means that there is a possibility to produce glitchs.

Is it necessery to smaple each gate's output by FF???

 

[ahmad_abdulghany]

Re: glitch

Assalaamo alaykom : )

In fact, I don't know what do u mean by the "gate's two outputs"! Doesn't the AND gate have only one output?

Or you have specific different case?

Clarify and correct me if i'm mistaken,

Best Wishes,
Ahmad,

 

[khaila]

Re: glitch

Assalaamo alaykom : )

In fact, I don't know what do u mean by the "gate's two outputs"! Doesn't the AND gate have only one output?

Or you have specific different case?

Clarify and correct me if i'm mistaken,

Best Wishes,
Ahmad,

Two output???
where do you see it.
I never wrote two outputs!!!
please re-notice!!

 

[ankit12345]

glitch

in a big combinational circuit with lots of gates..................
each gate will have some glitch........
but the required output will be stabe for longtime...........
the whole combi circuit output will toggle many times before settling to required state.........
its enough to have FF at the end of the combi ckt only........

if the combi is having too many gates..........glitch time is more.......which results is a clock with bigger timeperiod...........

 

[arp]

glitch

Since glitches may cause random o/p's, we use a flipflop at the o/p of a combi ckt.
as Ankit said u need to make sure that the o/p of an combi ckt need to be settled before the clk edge to avoid any random behavior!! that means ur clk period depends on this!!

 

[shivakumar043]

Re: glitch

Hi,

if your circuit is synchronous you need not warry

 

[yaseen1]

Re: glitch

This is because of different delays in gates

 

[shahal]

Re: glitch

If you have Asynchronous logic (YUCK!), and if your glitch does not violate the "pulse width" spec for your output logic, you should be OK, ie you will pass simulation, etc. However, this is bad because with deep sub-micron, OCV factors could cause on chip failures.

 

[khaila]

Re: glitch

PPL you don't answer my quastion.
I will explain my problem.

Let us considered AND gate with TWO inputs that is drived HIGH simulatnaly:
Actually the lenght's traces that drive both input are NOT equal.
Because the diffrente lenght of the traces the HIGH level will not drive the inputs excatlly at the time. Then always there is a posibality for glitches.

It is mean that I should sample each signal before driving the inputs.
Is it right???

 

[shahal]

Re: glitch

It is mean that I should sample each signal before driving the inputs.
Is it right???

Please help me understand, what do you mean by sample? If you know your pulses are of un-equal length, then yes you have glitch. I guess I have some questions:

1) are you trying to avoid glitches?
2) are you designing to add glitch?
3) are you testing an already existing circuit?

For the second case, I think its a bad design practice to design for glitches. More experienced designers can comment on that.

For the first case, you could maybe synchronise the inputs with a couple of flops, again more experienced designesr can comment better on this.

Finally, for the third case, what exactly are you trying to achieve?

 

[ankit12345]

glitch

The two input pins will have different capacetancess.
If u know that which input is having more load......
then if one of ur input is always coming faster than other...than connect the faster input to that pin with more load.
I think this happens rarly.

 

[NuttyAvatar]

glitch

Assuming the o/p finally drives a flop input, maybe Flop/latch the 2 inputs driving the gate using the negative edge of the clock?

 

[tdminion]

glitch

Just bored, thought I would respond. Glitches will always occur at the output an AND gate when the inputs are opposite and the 1->0 transition on input X occurs before the 0->1 transition on input Y (i.e. the pulldown network is briefly on). If the inputs change reasonably close in time, the turn-on time of the transistors will filter out the glitch. If you are relying on the output to never glitch....then you probably are not designing correctly.....or you need to hang out with Analog designers