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Even using sync design there can be scenarios that can produce glitches. Secondly all designs cannot be made complete synchronous. It will be good if other methods/ways are suggested.Use synchronous design. Use synchronizers when crossing clock domains.
Your original post asked how to write rtl that had no glitches. You said nothing about 'techniques being used to find out...'There are techniques being used to find out if a rtl which is written can produce glitch or not. Those techniques are used to see whether a rtl which is already written or being written can produce glitch or not. That is the reason for starting this thread with the query at post#1.
You are certainly entitled to your opinion, but if you have a long trace or wire on RTL then it's relevant.Your first statement just reinforces the concept of why synchronous logic DOESNT have a glitch.
The rest of your post has absolutely nothing to do with this discussion of glitches in rtl.
does not compute. RTL has no notion of long traces or wires.You are certainly entitled to your opinion, but if you have a long trace or wire on RTL then it's relevant.
I was just sharing the duality of the word "glitch". Even code eventually becomes analog.
Sorry to confuse you with these analogies of the word glitch into the analog domain, I'll try to avoid avoid these tangents.does not compute. RTL has no notion of long traces or wires.
you are mixing a lot of concepts. glitches due to logic switching are not the same as glitches due to crosstalk. no one would ever refer to a crosstalk glitch as an "RTL problem".
If you refer to the glitches emancipated from different path delays in combinatorial clouds (i.e. Multipliers), then totally eliminating glitches is impossible in gate-level. But you can write the code in a way glitches are minimized based on the information of some standard cell library components. i.e. You can define the booth encoder/decoder circuits of a Booth multiplier to be balanced (from AO/OA/AOI/OAI type of cells) and make them symmetrical. This however needs bit-level writing of your design instead of word-level operators.How can we take care such that when we write rtls, no glitch can occur from that rtl which is being coded?