Giving inputs to openfire cpu

[rockstar34]

i am working on openfire Risc cpu.. there is confusion in giving the inputs to verilog code of it because the whole code is linked with I/O peripherals. i am trying to check only the risc cpu.I isolated the cpu from the whole code but can not give the correct inputs. can anybody guide me?

 

[blooz]

i am working on openfire Risc cpu.. there is confusion in giving the inputs to verilog code of it because the whole code is linked with I/O peripherals. i am trying to check only the risc cpu.I isolated the cpu from the whole code but can not give the correct inputs. can anybody guide me?

The Best and Simplest Strategy would be debugging at subsystem level .....
ALU subsystem
Instruction Decoder Subsystem
Memory .....etc

Using a Test bench Excite the Corresponding Subsystems and verify the output signals are generated ....

---------- Post added at 17:15 ---------- Previous post was at 17:12 ----------

//Here is a simple example

Instruction Decoder
////////////////////////
//
// Copyright (c) 1999 Thomas Coonan (tcoonan@mindspring.com)
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//

module idec (
inst,
aluasel,
alubsel,
aluop,
wwe,
fwe,
zwe,
cwe,
bdpol,
option,
tris
);

input [11:0] inst;

output [1:0] aluasel;
output [1:0] alubsel;
output [3:0] aluop;
output wwe;
output fwe;
output zwe;
output cwe;
output bdpol;
output option;
output tris;

reg [14:0] decodes;

// For reference, the ALU Op codes are:
//
// ADD 0000
// SUB 1000
// AND 0001
// OR 0010
// XOR 0011
// COM 0100
// ROR 0101
// ROL 0110
// SWAP 0111
// MUL 1001

assign { aluasel, // Select source for ALU A input. 00=W, 01=SBUS, 10=K, 11=BD
alubsel, // Select source for ALU B input. 00=W, 01=SBUS, 10=K, 11="1"
aluop, // ALU Operation (see comments above for these codes)
wwe, // W register Write Enable
fwe, // File Register Write Enable
zwe, // Status register Z bit update
cwe, // Status register Z bit update
bdpol, // Polarity on bit decode vector (0=no inversion, 1=invert)
tris, // Instruction is an TRIS instruction
option // Instruction is an OPTION instruction
} = decodes;

// This is a large combinatorial decoder.
// I use the casex statement.

always @(inst) begin
casex (inst) // synopsys parallel_case
// *** Byte-Oriented File Register Operations
//
// A A ALU W F Z C B T O
// L L O W W W W D R P
// U U P E E E E P I T
// A B O S
// L
12'b0000_0000_0000: decodes = 15'b00_00_0000_0_0_0_0_0_0_0; // NOP
12'b0000_001X_XXXX: decodes = 15'b00_00_0010_0_1_0_0_0_0_0; // MOVWF
12'b0000_0100_0000: decodes = 15'b00_00_0011_1_0_1_0_0_0_0; // CLRW
12'b0000_011X_XXXX: decodes = 15'b00_00_0011_0_1_1_0_0_0_0; // CLRF
12'b0000_100X_XXXX: decodes = 15'b01_00_1000_1_0_1_1_0_0_0; // SUBWF (d=0)
12'b0000_101X_XXXX: decodes = 15'b01_00_1000_0_1_1_1_0_0_0; // SUBWF (d=1)
12'b0000_110X_XXXX: decodes = 15'b01_11_1000_1_0_1_0_0_0_0; // DECF (d=0)
12'b0000_111X_XXXX: decodes = 15'b01_11_1000_0_1_1_0_0_0_0; // DECF (d=1)
12'b0001_000X_XXXX: decodes = 15'b00_01_0010_1_0_1_0_0_0_0; // IORWF (d=0)
12'b0001_001X_XXXX: decodes = 15'b00_01_0010_0_1_1_0_0_0_0; // IORWF (d=1)
12'b0001_010X_XXXX: decodes = 15'b00_01_0001_1_0_1_0_0_0_0; // ANDWF (d=0)
12'b0001_011X_XXXX: decodes = 15'b00_01_0001_0_1_1_0_0_0_0; // ANDWF (d=1)
12'b0001_100X_XXXX: decodes = 15'b00_01_0011_1_0_1_0_0_0_0; // XORWF (d=0)
12'b0001_101X_XXXX: decodes = 15'b00_01_0011_0_1_1_0_0_0_0; // XORWF (d=1)
12'b0001_110X_XXXX: decodes = 15'b00_01_0000_1_0_1_1_0_0_0; // ADDWF (d=0)
12'b0001_111X_XXXX: decodes = 15'b00_01_0000_0_1_1_1_0_0_0; // ADDWF (d=1)
12'b0010_000X_XXXX: decodes = 15'b01_01_0010_1_0_1_0_0_0_0; // MOVF (d=0)
12'b0010_001X_XXXX: decodes = 15'b01_01_0010_0_1_1_0_0_0_0; // MOVF (d=1)
12'b0010_010X_XXXX: decodes = 15'b01_01_0100_1_0_1_0_0_0_0; // COMF (d=0)
12'b0010_011X_XXXX: decodes = 15'b01_01_0100_0_1_1_0_0_0_0; // COMF (d=1)
12'b0010_100X_XXXX: decodes = 15'b01_11_0000_1_0_1_0_0_0_0; // INCF (d=0)
12'b0010_101X_XXXX: decodes = 15'b01_11_0000_0_1_1_0_0_0_0; // INCF (d=1)
12'b0010_110X_XXXX: decodes = 15'b01_11_1000_1_0_0_0_0_0_0; // DECFSZ(d=0)
12'b0010_111X_XXXX: decodes = 15'b01_11_1000_0_1_0_0_0_0_0; // DECFSZ(d=1)
12'b0011_000X_XXXX: decodes = 15'b01_01_0101_1_0_0_1_0_0_0; // RRF (d=0)
12'b0011_001X_XXXX: decodes = 15'b01_01_0101_0_1_0_1_0_0_0; // RRF (d=1)
12'b0011_010X_XXXX: decodes = 15'b01_01_0110_1_0_0_1_0_0_0; // RLF (d=0)
12'b0011_011X_XXXX: decodes = 15'b01_01_0110_0_1_0_1_0_0_0; // RLF (d=1)
12'b0011_100X_XXXX: decodes = 15'b01_01_0111_1_0_0_0_0_0_0; // SWAPF (d=0)
12'b0011_101X_XXXX: decodes = 15'b01_01_0111_0_1_0_0_0_0_0; // SWAPF (d=1)
12'b0011_110X_XXXX: decodes = 15'b01_11_0000_1_0_0_0_0_0_0; // INCFSZ(d=0)
12'b0011_1111_0XXX: decodes = 15'b01_11_0000_0_1_0_0_0_0_0; // INCFSZ(d=1)
12'b0011_1111_1XXX: decodes = 15'b00_01_1001_0_0_1_1_0_0_0;
// *** Bit-Oriented File Register Operations
//
// A A ALU W F Z C B T O
// L L O W W W W D R P
// U U P E E E E P I T
// A B O S
// L
12'b0100_XXXX_XXXX: decodes = 15'b11_01_0001_0_1_0_0_1_0_0; // BCF
12'b0101_XXXX_XXXX: decodes = 15'b11_01_0010_0_1_0_0_0_0_0; // BSF
12'b0110_XXXX_XXXX: decodes = 15'b11_01_0001_0_0_0_0_0_0_0; // BTFSC
12'b0111_XXXX_XXXX: decodes = 15'b11_01_0001_0_0_0_0_0_0_0; // BTFSS

// *** Literal and Control Operations
//
// A A ALU W F Z C B T O
// L L O W W W W D R P
// U U P E E E E P I T
// A B O S
// L
12'b0000_0000_0010: decodes = 15'b00_00_0010_0_1_0_0_0_0_1; // OPTION
12'b0000_0000_0011: decodes = 15'b00_00_0000_0_0_0_0_0_0_0; // SLEEP
12'b0000_0000_0100: decodes = 15'b00_00_0000_0_0_0_0_0_0_0; // CLRWDT
12'b0000_0000_0101: decodes = 15'b00_00_0000_0_1_0_0_0_1_0; // TRIS 5
12'b0000_0000_0110: decodes = 15'b00_00_0010_0_1_0_0_0_1_0; // TRIS 6
12'b0000_0000_0111: decodes = 15'b00_00_0010_0_1_0_0_0_1_0; // TRIS 7
//
// A A ALU W F Z C B T O
// L L O W W W W D R P
// U U P E E E E P I T
// A B O S
// L
12'b1000_XXXX_XXXX: decodes = 15'b10_10_0010_1_0_0_0_0_0_0; // RETLW
12'b1001_XXXX_XXXX: decodes = 15'b10_10_0010_0_0_0_0_0_0_0; // CALL
12'b101X_XXXX_XXXX: decodes = 15'b10_10_0010_0_0_0_0_0_0_0; // GOTO
12'b1100_XXXX_XXXX: decodes = 15'b10_10_0010_1_0_0_0_0_0_0; // MOVLW
12'b1101_XXXX_XXXX: decodes = 15'b00_10_0010_1_0_1_0_0_0_0; // IORLW
12'b1110_XXXX_XXXX: decodes = 15'b00_10_0001_1_0_1_0_0_0_0; // ANDLW
12'b1111_XXXX_XXXX: decodes = 15'b00_10_0011_1_0_1_0_0_0_0; // XORLW

default:
decodes = 15'b00_00_0000_0_0_0_0_0_0_0;
endcase
end

endmodule


///////////////////////

A simple test bench to check the functionality

////////////////////////

`timescale 1 ns / 1ns

module idec_tb ;
reg [11:0] inst0;
wire aluasel1;
wire alubsel1;
wire aluop1;
wire wwe1;
wire fwe1;
wire zwe1;
wire cwe1;
wire bdpol1;
wire option1;
wire tris1;
idec idec1 (
inst0,
aluasel1,
alubsel1,
aluop1,
wwe1,
fwe1,
zwe1,
cwe1,
bdpol1,
option1,
tris1
);

initial
begin
#10
inst0=12'b0000_001X_XXXX; // MOVWF
#10
inst0=12'b0000_0100_0000 ; //CLRW
#10
inst0=12'b0000_011X_XXXX; //CLRF
#10
inst0= 12'b0000_100X_XXXX; //SUBWF (D=0)
#10
inst0= 12'b0000_101X_XXXX;//SUBWF(D=1)
#10
inst0= 12'b0000_110X_XXXX;//DECF(D=0)
#10
inst0= 12'b0000_111X_XXXX;//DECF(D=1)
#10
inst0= 12'b0001_000X_XXXX; //IORWF(D=0)
#10
inst0= 12'b0001_001X_XXXX; //IORWF(D=1)
#10
inst0= 12'b0001_010X_XXXX;//ANDWF(D=0)
#10
inst0= 12'b0001_011X_XXXX;//ANDWF(D=1)
#10
inst0= 12'b0001_100X_XXXX;//XORWF (D=0)
#10
inst0= 12'b0001_101X_XXXX;//XORWF (D=1)
#10
inst0= 12'b0001_110X_XXXX;//ADDWF (D=0)
#10
inst0= 12'b0001_111X_XXXX;//ADDWF (D=1)
#10
inst0= 12'b0010_000X_XXXX;//MOVF (D=0)
#10
inst0= 12'b0010_001X_XXXX;//MOVF (D=1)
#10
inst0= 12'b0010_010X_XXXX;//COMF (D=0)
#10
inst0= 12'b0010_011X_XXXX;//COMF (D=1)
#10
inst0= 12'b0010_100X_XXXX;//INCF(D=0)
#10
inst0= 12'b0010_101X_XXXX;//INCF (D=1)
#10
inst0= 12'b0010_110X_XXXX;//DECFSZ (D=0)
#10
inst0= 12'b0010_111X_XXXX;//DECFSZ (D=1)
#10
inst0= 12'b0011_000X_XXXX;//RRF (D=0)
#10
inst0= 12'b0011_001X_XXXX;//RRF (D=1)
#10
inst0= 12'b0011_010X_XXXX;//RLF (D=0)
#10
inst0= 12'b0011_011X_XXXX;//RLF (D=1)
#10
inst0= 12'b0011_100X_XXXX;//SWAPF (D=0)
#10
inst0= 12'b0011_101X_XXXX ;//SWAPF (D=1)
#10
inst0= 12'b0011_110X_XXXX;//INCFSZ (D=0)
#10
inst0= 12'b0011_1111_0XXX;//MULAB
#10
inst0= 12'b0100_XXXX_XXXX;//BCF
#10
inst0= 12'b0101_XXXX_XXXX;//BSF
#10
inst0= 12'b0110_XXXX_XXXX;//BTFSC
#10
inst0= 12'b0111_XXXX_XXXX;//BTFSS
#10
inst0= 12'b0000_0000_0010;//OPTION
#10
inst0= 12'b0000_0000_0011;//SLEEP
#10
inst0= 12'b0000_0000_0100;//CLRWDT
#10
inst0= 12'b0000_0000_0101;//TRIS5
#10
inst0= 12'b0000_0000_0110 ; //TRIS6
#10
inst0= 12'b0000_0000_0111 ;//TRIS7
#10
inst0= 12'b1000_XXXX_XXXX;//RETLW
#10
inst0= 12'b1001_XXXX_XXXX;//CALL
#10
inst0= 12'b101X_XXXX_XXXX;//GOTO
#10
inst0= 12'b1100_XXXX_XXXX;//MOVLW
#10
inst0= 12'b1101_XXXX_XXXX;//IORLW
#10
inst0= 12'b1110_XXXX_XXXX;//ANDLW
#10
inst0= 12'b1111_XXXX_XXXX;//XORLW

end

endmodule
//////////////////////////////////

 

[rockstar34]

Thanks for replying my question and giving an eg.. Ya, i am trying to test the code from the sub-system.. i isolated the RIsc cpu from the I/O pheriperals, but got small doubt to write the test bench.HOw we can give the instruction memory (32 bit) to the cpu?

 

[blooz]

If you have to fetch the Instructions from Memory itself .Form a Memory and ...Place the Hex code of the Program at consecutive locations ...and Read that Memory ....

Memory can be formed in many ways a case Statement is simple in logic but ...gets too lengthy .....

A simple one

module instruction_memory (clk,din,dout,ce,wr,rd,addr);
//port declarations
//logic
Always @(posedge clk)
if (conditions ie(wr/rd) )
//read case
use a Switch case (Addr)

4'b0000: dout=data;


..........................
other wise use a ROM file ......As Instruction Memory
inside Test Bench Instantiate the Cpu ...and

read the ROM contents ....

here is a good thread on Memory

https://www.edaboard.com/threads/132154/